JPS56146333A - Signal identifying device - Google Patents
Signal identifying deviceInfo
- Publication number
- JPS56146333A JPS56146333A JP5016580A JP5016580A JPS56146333A JP S56146333 A JPS56146333 A JP S56146333A JP 5016580 A JP5016580 A JP 5016580A JP 5016580 A JP5016580 A JP 5016580A JP S56146333 A JPS56146333 A JP S56146333A
- Authority
- JP
- Japan
- Prior art keywords
- converter
- circuit
- symbol value
- supplied
- symbol
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L25/00—Baseband systems
- H04L25/02—Details ; arrangements for supplying electrical power along data transmission lines
- H04L25/03—Shaping networks in transmitter or receiver, e.g. adaptive shaping networks
- H04L25/03006—Arrangements for removing intersymbol interference
- H04L25/03012—Arrangements for removing intersymbol interference operating in the time domain
- H04L25/03114—Arrangements for removing intersymbol interference operating in the time domain non-adaptive, i.e. not adjustable, manually adjustable, or adjustable only during the reception of special signals
- H04L25/03133—Arrangements for removing intersymbol interference operating in the time domain non-adaptive, i.e. not adjustable, manually adjustable, or adjustable only during the reception of special signals with a non-recursive structure
Abstract
PURPOSE:To eliminate even an intercode interference on a transmission line having a nonlinear transmission characteristic, by defining the received signal on the nonlinear transmission line to a certain symbol value based on a prescribed value. CONSTITUTION:The base band received signal to be supplied to the input terminal 100 is sampled in a certain cycle and then converted into a digital signal by the A/D converter 2. The output code bit of the converter 2 shows a tentative decision result and is supplied to the 3-step shift register 3 which functions as a pattern presuming circuit. At the same time, the output of the converter 2 is sent to a digital subtractor 5, i.e., the final deciding circuit via a delay circuit 4 equivalent to a time slot. The symbol multiplier circuit 6 secures an exclusive OR between the outputs of registers 30-32 and the code bits of memories 60-62 via the elements 70-73 and thus obtains a symbol value. Then the symbol value of the final decision is obtained by the subtractor 5. In such way, the distortion can be eliminated.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP5016580A JPS56146333A (en) | 1980-04-15 | 1980-04-15 | Signal identifying device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP5016580A JPS56146333A (en) | 1980-04-15 | 1980-04-15 | Signal identifying device |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS56146333A true JPS56146333A (en) | 1981-11-13 |
Family
ID=12851584
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP5016580A Pending JPS56146333A (en) | 1980-04-15 | 1980-04-15 | Signal identifying device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS56146333A (en) |
-
1980
- 1980-04-15 JP JP5016580A patent/JPS56146333A/en active Pending
Similar Documents
Publication | Publication Date | Title |
---|---|---|
JPS5523603A (en) | Method and apparatus for coding and decoding of telephone signal | |
KR950035104A (en) | Data receiver, metric calculation method and signal processing device | |
KR850002374A (en) | Binary signal cutting devices | |
JPS5596751A (en) | Signal discrimination unit | |
US4646327A (en) | Waveform shaping apparatus | |
JPS6490618A (en) | High speed continuous approximation register in analog-to-digital converter | |
US3825924A (en) | Pulse code modulation code conversion | |
JPS56146333A (en) | Signal identifying device | |
GB1344107A (en) | Digital equalizers | |
US5463572A (en) | Multi-nary and logic device | |
US5463571A (en) | Multi-nary OR logic device | |
JPS56146334A (en) | Adaptive signal identifying device | |
JPS568915A (en) | Nonlinear distortion reducing circuit of digital filter | |
JPS52140241A (en) | Binary #-digit addition circuit | |
JPS61274425A (en) | Digital compressing curcuit | |
JPS56143051A (en) | Data shift circuit | |
JPS5797737A (en) | Nonlinear equalizer | |
JPS5713543A (en) | Data speed transducer | |
RU1785078C (en) | Byte-companding adaptive delta-modulator | |
JPS564911A (en) | Digital limiter | |
KR960007104Y1 (en) | D/a converter | |
JPS56115027A (en) | Signal converter | |
GB1528954A (en) | Digital attenuator | |
KR920701903A (en) | Method and apparatus for performing approximate arithmetic division | |
Milutinović | A 4800 bit/s microprocessor-based CCITT compatible data modem |