JPS56145431A - Address assigning system of microprocessor - Google Patents

Address assigning system of microprocessor

Info

Publication number
JPS56145431A
JPS56145431A JP4675680A JP4675680A JPS56145431A JP S56145431 A JPS56145431 A JP S56145431A JP 4675680 A JP4675680 A JP 4675680A JP 4675680 A JP4675680 A JP 4675680A JP S56145431 A JPS56145431 A JP S56145431A
Authority
JP
Japan
Prior art keywords
cpu100
address
signal
microprocessor
switch
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP4675680A
Other languages
Japanese (ja)
Inventor
Mitsuhiro Kaneyasu
Haruhiko Tomono
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Tokyo Shibaura Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp, Tokyo Shibaura Electric Co Ltd filed Critical Toshiba Corp
Priority to JP4675680A priority Critical patent/JPS56145431A/en
Publication of JPS56145431A publication Critical patent/JPS56145431A/en
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/36—Preventing errors by testing or debugging software

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Quality & Reliability (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Debugging And Monitoring (AREA)

Abstract

PURPOSE:To facilitate the debugging of a program, by enabling the start of the program at an optional address assigned by a switch by adding the switch and logic to a microprocessor. CONSTITUTION:Microprocessor CPU100 generates reset-out signal 23 synchronizing with reset-in signal 24 generated when an address assigning switch provided to debugging panel 102, and at the 1st timing after signal 23 is ceased, CPU100 starts operation. As a result of the operation start, a memory address is sent from CPU100 to memory device 101 and an unconditional branch instruction from device 101 is received by CPU100 via data bus 10 corresponding to the timing of RD signal 21. Then, CPU100 decodes the instruction to inhibit access to device 101 according to the set state of the change-over switch on debugging panel 102, and then when the access to device 101 is enabled by setting the jump-destination address of panel 102, the program is started at an optional address.
JP4675680A 1980-04-11 1980-04-11 Address assigning system of microprocessor Pending JPS56145431A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP4675680A JPS56145431A (en) 1980-04-11 1980-04-11 Address assigning system of microprocessor

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP4675680A JPS56145431A (en) 1980-04-11 1980-04-11 Address assigning system of microprocessor

Publications (1)

Publication Number Publication Date
JPS56145431A true JPS56145431A (en) 1981-11-12

Family

ID=12756162

Family Applications (1)

Application Number Title Priority Date Filing Date
JP4675680A Pending JPS56145431A (en) 1980-04-11 1980-04-11 Address assigning system of microprocessor

Country Status (1)

Country Link
JP (1) JPS56145431A (en)

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