JPS56144655A - Character-multiplex system time-division multiplexer - Google Patents

Character-multiplex system time-division multiplexer

Info

Publication number
JPS56144655A
JPS56144655A JP4812780A JP4812780A JPS56144655A JP S56144655 A JPS56144655 A JP S56144655A JP 4812780 A JP4812780 A JP 4812780A JP 4812780 A JP4812780 A JP 4812780A JP S56144655 A JPS56144655 A JP S56144655A
Authority
JP
Japan
Prior art keywords
break
flop
flip
character
division multiplexer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP4812780A
Other languages
English (en)
Japanese (ja)
Other versions
JPS637496B2 (enrdf_load_stackoverflow
Inventor
Hiroichi Otsuka
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP4812780A priority Critical patent/JPS56144655A/ja
Publication of JPS56144655A publication Critical patent/JPS56144655A/ja
Publication of JPS637496B2 publication Critical patent/JPS637496B2/ja
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H04L7/04—Speed or phase control by synchronisation signals
    • H04L7/041—Speed or phase control by synchronisation signals using special codes as synchronising signal
    • H04L7/044—Speed or phase control by synchronisation signals using special codes as synchronising signal using a single bit, e.g. start stop bit

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Time-Division Multiplex Systems (AREA)
JP4812780A 1980-04-14 1980-04-14 Character-multiplex system time-division multiplexer Granted JPS56144655A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP4812780A JPS56144655A (en) 1980-04-14 1980-04-14 Character-multiplex system time-division multiplexer

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP4812780A JPS56144655A (en) 1980-04-14 1980-04-14 Character-multiplex system time-division multiplexer

Publications (2)

Publication Number Publication Date
JPS56144655A true JPS56144655A (en) 1981-11-11
JPS637496B2 JPS637496B2 (enrdf_load_stackoverflow) 1988-02-17

Family

ID=12794653

Family Applications (1)

Application Number Title Priority Date Filing Date
JP4812780A Granted JPS56144655A (en) 1980-04-14 1980-04-14 Character-multiplex system time-division multiplexer

Country Status (1)

Country Link
JP (1) JPS56144655A (enrdf_load_stackoverflow)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63106059A (ja) * 1986-08-01 1988-05-11 ジェネラル　デイタコム　インコーポレーテッド マルチノ−ド通信システム用高速ビット・インタ−リ−ブド時分割マルチプレクサ

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63106059A (ja) * 1986-08-01 1988-05-11 ジェネラル　デイタコム　インコーポレーテッド マルチノ−ド通信システム用高速ビット・インタ−リ−ブド時分割マルチプレクサ

Also Published As

Publication number Publication date
JPS637496B2 (enrdf_load_stackoverflow) 1988-02-17

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