JPS56137667A - Self substrate bias circuit - Google Patents

Self substrate bias circuit

Info

Publication number
JPS56137667A
JPS56137667A JP4069880A JP4069880A JPS56137667A JP S56137667 A JPS56137667 A JP S56137667A JP 4069880 A JP4069880 A JP 4069880A JP 4069880 A JP4069880 A JP 4069880A JP S56137667 A JPS56137667 A JP S56137667A
Authority
JP
Japan
Prior art keywords
substrate bias
oscillation
fet
potential
self
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP4069880A
Other languages
Japanese (ja)
Inventor
Hideo Noguchi
Tsuginari Iwamoto
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Tokyo Shibaura Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp, Tokyo Shibaura Electric Co Ltd filed Critical Toshiba Corp
Priority to JP4069880A priority Critical patent/JPS56137667A/en
Publication of JPS56137667A publication Critical patent/JPS56137667A/en
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G05—CONTROLLING; REGULATING
    • G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
    • G05F3/00—Non-retroactive systems for regulating electric variables by using an uncontrolled element, or an uncontrolled combination of elements, such element or such combination having self-regulating properties
    • G05F3/02—Regulating voltage or current
    • G05F3/08—Regulating voltage or current wherein the variable is dc
    • G05F3/10—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics
    • G05F3/16—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics being semiconductor devices
    • G05F3/20—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics being semiconductor devices using diode- transistor combinations
    • G05F3/205—Substrate bias-voltage generators

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Nonlinear Science (AREA)
  • Electromagnetism (AREA)
  • General Physics & Mathematics (AREA)
  • Radar, Positioning & Navigation (AREA)
  • Automation & Control Theory (AREA)
  • Semiconductor Integrated Circuits (AREA)

Abstract

PURPOSE:To arrange so that a substrate bias effect may be obtained and at the same time, FET properties be stabilized by applying a self substrate bias during an oscillation and automatically a substrate potential at the level of an earthing potential when an oscillation is suspended. CONSTITUTION:If the threshold level of an enhancement-type FET1 is lower than the potential of a connection point A, FET1 is switched on, resulting in the subsequent switching of FET's 2, 3 in ''ON'' position. This action triggers the oscillation of a ring oscillator for a charge pump circuit 10 and a self substrate bias is applied normally, thus enabling a substrate bias effect to be realized. At that time, FET's 4, 6, 8, 9 are operated in an off on off fashion and even if an electric potential were applied on a drain on FET9, no adverse effect is created because FET9 is not electrified. On the contrary, if the threshold level of FET1 is higher than the electric potential of the connection point A, FET is thrown into ''OFF'' condition, suspending the oscillation of the ring oscillator and eliminating the application of a self substrate bias. In this case, FET9 is switched on, maintaining the substrate at an earthing level.
JP4069880A 1980-03-29 1980-03-29 Self substrate bias circuit Pending JPS56137667A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP4069880A JPS56137667A (en) 1980-03-29 1980-03-29 Self substrate bias circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP4069880A JPS56137667A (en) 1980-03-29 1980-03-29 Self substrate bias circuit

Publications (1)

Publication Number Publication Date
JPS56137667A true JPS56137667A (en) 1981-10-27

Family

ID=12587775

Family Applications (1)

Application Number Title Priority Date Filing Date
JP4069880A Pending JPS56137667A (en) 1980-03-29 1980-03-29 Self substrate bias circuit

Country Status (1)

Country Link
JP (1) JPS56137667A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6058658A (en) * 1983-09-12 1985-04-04 Hitachi Ltd Cmos integrated circuit device and inspecting method thereof
JPS63255957A (en) * 1987-04-13 1988-10-24 Mitsubishi Electric Corp Semiconductor integrated circuit device

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS54148492A (en) * 1978-05-15 1979-11-20 Nec Corp Integrated circuit

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS54148492A (en) * 1978-05-15 1979-11-20 Nec Corp Integrated circuit

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6058658A (en) * 1983-09-12 1985-04-04 Hitachi Ltd Cmos integrated circuit device and inspecting method thereof
JPS63255957A (en) * 1987-04-13 1988-10-24 Mitsubishi Electric Corp Semiconductor integrated circuit device

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