JPS56132650A - Control circuit for access inhibition - Google Patents
Control circuit for access inhibitionInfo
- Publication number
- JPS56132650A JPS56132650A JP3646680A JP3646680A JPS56132650A JP S56132650 A JPS56132650 A JP S56132650A JP 3646680 A JP3646680 A JP 3646680A JP 3646680 A JP3646680 A JP 3646680A JP S56132650 A JPS56132650 A JP S56132650A
- Authority
- JP
- Japan
- Prior art keywords
- address
- main memory
- discrimination
- bits
- access
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/14—Protection against unauthorised use of memory or access to memory
- G06F12/1416—Protection against unauthorised use of memory or access to memory by checking the object accessibility, e.g. type of access defined by the memory independently of subject rights
- G06F12/1425—Protection against unauthorised use of memory or access to memory by checking the object accessibility, e.g. type of access defined by the memory independently of subject rights the protection being physical, e.g. cell, word, block
- G06F12/1441—Protection against unauthorised use of memory or access to memory by checking the object accessibility, e.g. type of access defined by the memory independently of subject rights the protection being physical, e.g. cell, word, block for a range
Abstract
PURPOSE:To save the number of integrated circuits, by producing the access inhibition signal to the main storage device with the discrimination signal from the 2nd address of the main memory address and the 1st address. CONSTITUTION:The value of the 2nd address A2 stored in the 2nd address register 6 storing the lower 8-bits of the main memory address is fed to the read only memory circuit 7 to pick up one bit discrimination signal M and to give it to the discrimination circuit 8. Further, the 1st address A1 stored in the 1st address register 5 storing the upper tank 4-bits of the main memory address is read out and it is fed to the discrimination circuit 8, and the access inhibition signal D of logic 1 which inhibits the access to the main memory device only when 5-bits and 1-bit of the discrimination signal M are all zero, is output. Thus, the main memory address consisting of the 1st address A1 and the 2nd address can discriminate the boundary address.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP3646680A JPS56132650A (en) | 1980-03-21 | 1980-03-21 | Control circuit for access inhibition |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP3646680A JPS56132650A (en) | 1980-03-21 | 1980-03-21 | Control circuit for access inhibition |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS56132650A true JPS56132650A (en) | 1981-10-17 |
Family
ID=12470582
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP3646680A Pending JPS56132650A (en) | 1980-03-21 | 1980-03-21 | Control circuit for access inhibition |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS56132650A (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7864151B1 (en) | 1986-07-07 | 2011-01-04 | Semiconductor Energy Laboratory Co., Ltd. | Portable electronic device |
-
1980
- 1980-03-21 JP JP3646680A patent/JPS56132650A/en active Pending
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7864151B1 (en) | 1986-07-07 | 2011-01-04 | Semiconductor Energy Laboratory Co., Ltd. | Portable electronic device |
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