JPS56132066A - Television receiver - Google Patents

Television receiver

Info

Publication number
JPS56132066A
JPS56132066A JP3531780A JP3531780A JPS56132066A JP S56132066 A JPS56132066 A JP S56132066A JP 3531780 A JP3531780 A JP 3531780A JP 3531780 A JP3531780 A JP 3531780A JP S56132066 A JPS56132066 A JP S56132066A
Authority
JP
Japan
Prior art keywords
picture
blocks
controllers
signals
written
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP3531780A
Other languages
Japanese (ja)
Inventor
Masaaki Fujita
Minoru Ueda
Kazumi Kawashima
Hirosuke Yamamoto
Hidekazu Taira
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Priority to JP3531780A priority Critical patent/JPS56132066A/en
Publication of JPS56132066A publication Critical patent/JPS56132066A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04NPICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N5/00Details of television systems
    • H04N5/44Receiver circuitry for the reception of television signals according to analogue transmission standards

Landscapes

  • Engineering & Computer Science (AREA)
  • Multimedia (AREA)
  • Signal Processing (AREA)

Abstract

PURPOSE:To use the small-capacity and low-speed picture memory block to display one picture large, by writing picture signals of respective parts of the TV picture corresponding to one-screen components in plural picture memory blocks. CONSTITUTION:Picture signals received by one receiving circuit 2a are applied to picture memory blocks 1a-1d commonly, and write controllers 6a-6d are controlled by the clock signal from one write clock generating circuit 7a. Timings when respective parts are written in blocks 1a-1d are set by controllers 6a-6d. For example, when the control signal is input from terminal 14, signals of the first half and the latter half of one field and the first half and the latter half of one line are output and written by controlling controllers 5a-5d. Picture signals are read out continuously from blocks 1a-1d successively to display one picture large.
JP3531780A 1980-03-19 1980-03-19 Television receiver Pending JPS56132066A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP3531780A JPS56132066A (en) 1980-03-19 1980-03-19 Television receiver

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP3531780A JPS56132066A (en) 1980-03-19 1980-03-19 Television receiver

Publications (1)

Publication Number Publication Date
JPS56132066A true JPS56132066A (en) 1981-10-16

Family

ID=12438422

Family Applications (1)

Application Number Title Priority Date Filing Date
JP3531780A Pending JPS56132066A (en) 1980-03-19 1980-03-19 Television receiver

Country Status (1)

Country Link
JP (1) JPS56132066A (en)

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