JPS56127996A - Semiconductor circuit - Google Patents

Semiconductor circuit

Info

Publication number
JPS56127996A
JPS56127996A JP2997880A JP2997880A JPS56127996A JP S56127996 A JPS56127996 A JP S56127996A JP 2997880 A JP2997880 A JP 2997880A JP 2997880 A JP2997880 A JP 2997880A JP S56127996 A JPS56127996 A JP S56127996A
Authority
JP
Japan
Prior art keywords
memory
discharge
rom
time
discharge time
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP2997880A
Other languages
Japanese (ja)
Other versions
JPS6032917B2 (en
Inventor
Toshiaki Hoshi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP55029978A priority Critical patent/JPS6032917B2/en
Publication of JPS56127996A publication Critical patent/JPS56127996A/en
Publication of JPS6032917B2 publication Critical patent/JPS6032917B2/en
Expired legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C17/00—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards
    • G11C17/08—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards using semiconductor devices, e.g. bipolar elements
    • G11C17/10—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards using semiconductor devices, e.g. bipolar elements in which contents are determined during manufacturing by a predetermined arrangement of coupling elements, e.g. mask-programmable ROM
    • G11C17/12—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards using semiconductor devices, e.g. bipolar elements in which contents are determined during manufacturing by a predetermined arrangement of coupling elements, e.g. mask-programmable ROM using field-effect devices
    • G11C17/123—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards using semiconductor devices, e.g. bipolar elements in which contents are determined during manufacturing by a predetermined arrangement of coupling elements, e.g. mask-programmable ROM using field-effect devices comprising cells having several storage transistors connected in series

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Read Only Memory (AREA)
  • Pulse Circuits (AREA)
  • Electronic Switches (AREA)

Abstract

PURPOSE:To obtain a ROM which is steady with no reduction of the working speed, by separating a memory output line from a data latch via a delaying circuit having the maximum discharge time of the memmory output or the longer discharge time. CONSTITUTION:The sense output B1 caused by a discharge given via the sense amplifying inverter S of a memory cell containing the IGFETM1- connected in series is latched at the SD-type flip-flop FF. A pseudo cell array delaying circuit which conducts constantly is formed by the serial IGFETQv plus Q1- that have the longer stage number and the same arrangement pitch than the as the serial IGFETM1- of a memory cell having the longest discharge time of the ROM in which the above- mentioned memory cells are stacked in multiple stages. Thus the width of the latch clock phid, which has the sampling time to separate the inverter S from the FFF and is based on the delay discharge detection signal D obtained via the sense amplifying inverter S', becomes as the longest memory discharge time sampling time holding breakdown time of the shortest memory. As a result, a steady ROM can be obtained with no reduction of the working speed.
JP55029978A 1980-03-10 1980-03-10 semiconductor circuit Expired JPS6032917B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP55029978A JPS6032917B2 (en) 1980-03-10 1980-03-10 semiconductor circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP55029978A JPS6032917B2 (en) 1980-03-10 1980-03-10 semiconductor circuit

Publications (2)

Publication Number Publication Date
JPS56127996A true JPS56127996A (en) 1981-10-07
JPS6032917B2 JPS6032917B2 (en) 1985-07-31

Family

ID=12291043

Family Applications (1)

Application Number Title Priority Date Filing Date
JP55029978A Expired JPS6032917B2 (en) 1980-03-10 1980-03-10 semiconductor circuit

Country Status (1)

Country Link
JP (1) JPS6032917B2 (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60125998A (en) * 1983-12-12 1985-07-05 Fujitsu Ltd Semiconductor storage device
JPS61148696A (en) * 1984-12-22 1986-07-07 Nippon Texas Instr Kk Semiconductor storage device
JPS61150193A (en) * 1984-12-24 1986-07-08 Toshiba Corp Latch circuit

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60125998A (en) * 1983-12-12 1985-07-05 Fujitsu Ltd Semiconductor storage device
JPH0140437B2 (en) * 1983-12-12 1989-08-29 Fujitsu Ltd
JPS61148696A (en) * 1984-12-22 1986-07-07 Nippon Texas Instr Kk Semiconductor storage device
JPS61150193A (en) * 1984-12-24 1986-07-08 Toshiba Corp Latch circuit

Also Published As

Publication number Publication date
JPS6032917B2 (en) 1985-07-31

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