JPS6032917B2 - semiconductor circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a semiconductor read-only memory (hereinafter referred to as ROM), and in particular, to a semiconductor read-only memory (hereinafter referred to as ROM), a plurality of insulated gate field effect transistors (hereinafter referred to as MIS) are connected to one memory line.
The present invention relates to a so-called vertical ROM in which FETs (hereinafter simply referred to as FETs) are connected in series.

In recent years, in order to improve the degree of integration, ROMs with a vertical configuration and a ratioless configuration are often used, and in particular, they are used as internal ROMs in chips of microcomputers, electronic desk calculators, etc. There are many.

Most complementary insulated gate field effect transistors (hereinafter referred to as CMOS) with relatively low operating frequencies have the above-mentioned vertical ratioless configuration. As a normal means of increasing the degree of integration in vertical configurations,
One example of this is to increase the number of memory cells connected in series to one memory line.

In such a vertical ROM, as the number of memory cells connected in series increases, the impedance increases and the time required for precharging and discharging increases.
Complementary MOS (C/MOS) with conventional vertical ratioless configuration
) An example of a ROM using a FET is shown in FIG. 1, and an outline of its operation will be explained in terms of positive power supply and positive logic, with reference to timing and response characteristics in FIG.

Figure 1 is an example of a vertical ratioless NAND logic ROM.
12 pegs, 11 columns - When the number of vertical stacks of memory cells is small (for example, 10 to 2M), these logical operations are performed normally, but as the number of vertical stacks increases, the equivalent impedance of the memory cells decreases. becomes large, and the time required for precharging, especially when subjected to back bias, increases exponentially. Therefore, within the specified pre-IJ charging time, all series-connected memory cells are in a pinch-off state. It becomes impossible to charge the battery sufficiently.

If the ROM is accessed in such a state, the following problems will occur.

In other words, when ■p becomes "1" and ■s becomes "1" and the sampling state is entered, each node of the memory cell that could not be pinched off has a potential as shown in "Hold" of the response characteristic in Figure 2. Balance should be achieved. (The charge moves and the output Out must also be held, but the potential is gradually balanced, and eventually the information is destroyed and the sense amplifier detects reverse logic. “Discharge”
Even in this state, as the number of vertically stacked stacks increases, the equivalent impedance increases, so the time required for discharging increases. Under such conditions, as the number of vertical bond stages increases, the time required for data destruction in the retained state and the discharge time become considerably closer. (2)p and (2)s always use clocks synchronized with the internal basic clock, and it is difficult to obtain a reasonable sampling time that satisfies discharge time≦sampling time≦holding/destruction time in the frequency range where operation is to be guaranteed. In addition, when wide-ranging power supply fluctuations, temperature fluctuations, and fluctuations in manufacturing conditions are included, the discharge time and hold breakdown time under the worst conditions become closer and closer together. The "1" level is destroyed and the reverse logic is read into the latch circuit F. The purpose of this invention is to provide a ratioless RO system that is stable and does not reduce operating speed.
The purpose of this invention is to provide an M circuit.

The ROM according to the present invention is provided with a delay circuit having a bit that requires the longest discharge time or a slightly longer discharge time, and a signal that detects that the delay circuit has discharged is used to control the bit between the memory output and the sense amplifier. ~A feature is that by electrically separating the data latch circuit, destruction of the ``retention'' logic inside the memory circuit can be ignored.

An embodiment of this invention is shown in FIG.

In Figure 3, M, ~A, and spots are memory cell arrays of N-channel FETs in 1 row and 12 groups, Mp is a P-channel MISFET for pre-charge, Ma is an N-channel MISFET for sampling, and S is a sense Inverter for amplifier, F is SD flippf for data latch. It's Tsupu. Qr, Q, ~Q64~, 28 are N-channel cell arrays that are permanently turned on, Qp is P for precharging.
The channel type MISFET Qd is an N-channel type MISFET for sampling, S' is an inverter for a sense amplifier, and the s signal is inverted by INV and detected by a two-input NOR to obtain d.

SD for data latch with this ■d output and ■p output which is in reverse phase.
Controls flip-flop reading and feedback transfer gates. The P-channel substrate is connected to 10 Vcc, and the N-channel substrate is connected to ground potential. This will be explained using the response characteristics shown in FIG. 4 using positive power supply and positive logic. Sense output of memory circuit of 1st column-128th row B. has exactly the same timing and characteristics as explained in the conventional example.

The difference is that a delay circuit generates a latch clock used to read the flip-flop that latches this sense output and to control the feedback transfer gate. The width of the latch clocks ■d and ■d, that is, the sampling time, is set so that the longest memory discharge time≦sampling time≦the shortest memory retention and destruction time.

The circuit shown in FIG. 3 is a circuit that easily satisfies this condition. A permanently conductive pseudo cell array is arranged in line with the memory cell array. If the cell size and array pitch are kept the same and the number of series stages is slightly larger than the longest number of stages in the memory circuit, the sampling time can be set as short as possible while always being longer than the longest memory discharge time. This is advantageous because changes in on-resistance and capacitance of the cell size due to manufacturing conditions, power supply fluctuations, temperature changes, etc. will affect the memory cell array and delay circuit simultaneously.

In this way, no matter what the basic clock s becomes, the sampling latch clock is always determined by the discharge time of the delay circuit. After the delay circuit is discharged (■d is “0”), the read transfer of the data latch flip-flop is cut off and the memory output and the read transfer of the flip-flop are cut off and the memory output In order to separate the flip-flop and the flip-flop, it does not matter what happens to the subsequent destruction of "retained" information on the memory cell side. In the above explanation, the configuration of the ROM is one bit output, and each bit has one column and 12 squares.
It doesn't matter if it has multiple lines.

Further, in the above description, if the voltage polarity is reversed, the channel type may also be reversed, and it is also possible to use a single channel such as P channel or N channel instead of CMOS.

Brief explanation of the drawings Figure 1 shows the ratioless configuration ROM of subordinates.
Figure 2 is a diagram showing an example of the bit configuration of column 1-12 of
FIG. 1 is a diagram showing the response characteristics of the timing clock used in the conventional circuit and each node potential, FIG. 3 is a diagram showing a circuit example of the ratioless ROM of the present invention using a delay circuit, and FIG. 4 is a diagram showing the response characteristics of the timing clock used in the conventional circuit. FIG. 4 is a diagram showing the response characteristics of the timing clock used as the clock used, the memory and each node potential of the delay circuit, and the latch clock irregular shape.

Mp...Precharge FET, M, ~M64~M
, 2... Memory cell FET, SD...
Flip Frotzf〇.

inferior figure Figure 4 Plan Z diagram Figure 3

Claims (1)

[Claims] 1. A circuit comprising a read-only memory with a vertical ratioless configuration in which a plurality of insulated gate field effect transistors are connected in series, and a delay circuit with a vertical ratioless configuration that charges and discharges in synchronization with the read-only memory. The discharge time of the delay circuit is equal to or longer than the longest discharge time of the memory output, and a signal detecting discharge of the delay circuit connects the memory output line and the data latch circuit electrically. A semiconductor circuit characterized by being separated into two.