JPS56126388A - Receiver of character information - Google Patents

Receiver of character information

Info

Publication number
JPS56126388A
JPS56126388A JP3120080A JP3120080A JPS56126388A JP S56126388 A JPS56126388 A JP S56126388A JP 3120080 A JP3120080 A JP 3120080A JP 3120080 A JP3120080 A JP 3120080A JP S56126388 A JPS56126388 A JP S56126388A
Authority
JP
Japan
Prior art keywords
memory
output
bits
circuit
receiver
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP3120080A
Other languages
Japanese (ja)
Other versions
JPH0143512B2 (en
Inventor
Masayoshi Hirashima
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Priority to JP3120080A priority Critical patent/JPS56126388A/en
Publication of JPS56126388A publication Critical patent/JPS56126388A/en
Publication of JPH0143512B2 publication Critical patent/JPH0143512B2/ja
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N7/00—Television systems
    • H04N7/08—Systems for the simultaneous or sequential transmission of more than one television signal, e.g. additional information signals, the signals occupying wholly or partially the same frequency band, e.g. by time division
    • H04N7/087—Systems for the simultaneous or sequential transmission of more than one television signal, e.g. additional information signals, the signals occupying wholly or partially the same frequency band, e.g. by time division with signal insertion during the vertical blanking interval only
    • H04N7/088—Systems for the simultaneous or sequential transmission of more than one television signal, e.g. additional information signals, the signals occupying wholly or partially the same frequency band, e.g. by time division with signal insertion during the vertical blanking interval only the inserted signal being digital
    • H04N7/0887—Systems for the simultaneous or sequential transmission of more than one television signal, e.g. additional information signals, the signals occupying wholly or partially the same frequency band, e.g. by time division with signal insertion during the vertical blanking interval only the inserted signal being digital for the transmission of programme or channel identifying signals

Landscapes

  • Engineering & Computer Science (AREA)
  • Multimedia (AREA)
  • Signal Processing (AREA)
  • Television Systems (AREA)

Abstract

PURPOSE:To ensure an easy use of a receiver of character information by sending not only the screen information but the program code and then storing this program code together with the screen information at the receiver side. CONSTITUTION:When the framing code FC is detected out of the output of the sampling circuit 3, the clock gate 5 resets a dividing circuit of the output of the gate 5 to lock the phase at that of the transmitted signal. Thus an accurate sampling is possible. The output of the circuit 3 is read at the write/read control circuit 7, and only the screen of the program selected by the selection switch 11 is written into the main memory 8. The output of the memory 8 is amplified by the buffer amplifier 9 to be displayed at the CRT10. Here, for instance, 16 screens, i.e., 820K bits are provided to the memory 8 to ensure an application of a multi-page memory. In this case, the control circuit 7 control the memory 8 so that the memory stores 256 bits in all (8 information bits and 248 character pattern bits) regardless of the designation of the selection switch 11.
JP3120080A 1980-03-11 1980-03-11 Receiver of character information Granted JPS56126388A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP3120080A JPS56126388A (en) 1980-03-11 1980-03-11 Receiver of character information

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP3120080A JPS56126388A (en) 1980-03-11 1980-03-11 Receiver of character information

Publications (2)

Publication Number Publication Date
JPS56126388A true JPS56126388A (en) 1981-10-03
JPH0143512B2 JPH0143512B2 (en) 1989-09-21

Family

ID=12324769

Family Applications (1)

Application Number Title Priority Date Filing Date
JP3120080A Granted JPS56126388A (en) 1980-03-11 1980-03-11 Receiver of character information

Country Status (1)

Country Link
JP (1) JPS56126388A (en)

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5662490A (en) * 1979-10-26 1981-05-28 Sanyo Electric Co Ltd Television receiver for character multiplex broadcasting

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5662490A (en) * 1979-10-26 1981-05-28 Sanyo Electric Co Ltd Television receiver for character multiplex broadcasting

Also Published As

Publication number Publication date
JPH0143512B2 (en) 1989-09-21

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