JPS56121131A - Dma control system - Google Patents

Dma control system

Info

Publication number
JPS56121131A
JPS56121131A JP2459580A JP2459580A JPS56121131A JP S56121131 A JPS56121131 A JP S56121131A JP 2459580 A JP2459580 A JP 2459580A JP 2459580 A JP2459580 A JP 2459580A JP S56121131 A JPS56121131 A JP S56121131A
Authority
JP
Japan
Prior art keywords
data
register
transfer
transfer unit
unit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP2459580A
Other languages
Japanese (ja)
Other versions
JPS5932814B2 (en
Inventor
Tadaaki Imai
Masaaki Kobayashi
Kanzo Noda
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP2459580A priority Critical patent/JPS5932814B2/en
Publication of JPS56121131A publication Critical patent/JPS56121131A/en
Publication of JPS5932814B2 publication Critical patent/JPS5932814B2/en
Expired legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/20—Handling requests for interconnection or transfer for access to input/output bus
    • G06F13/28—Handling requests for interconnection or transfer for access to input/output bus using burst mode transfer, e.g. direct memory access DMA, cycle steal

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Bus Control (AREA)

Abstract

PURPOSE:To eliminate the need for a data register and to shorten the processing time, by enabling data transfer by assigning the transfer unit of data in a control register. CONSTITUTION:Data transfer between main memory device 1 and channel device 4 for files has the four-byte unit and 256-type unit. For example, when data are written in device 1 in 256-byte unit mode, subordinate processor 5 sets signal 1 in write start bit field (w) and transfer unit assignment field (b) in control register R1 and starts direct memory acess control. Consequently, data (d) in file device 6 are fetched by 256 bits at every time and written in device 1. When data are read out of device 1, signal 1 is set in field (r) in register R1 and when the transfer unit is four bytes, signal 1 is only set in transfer unit assignment field (a). Consequently, the data register is unnecessary and the processing steps of device 5 are reduced, so that the processing time will be shortened.
JP2459580A 1980-02-28 1980-02-28 DMA control method Expired JPS5932814B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2459580A JPS5932814B2 (en) 1980-02-28 1980-02-28 DMA control method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2459580A JPS5932814B2 (en) 1980-02-28 1980-02-28 DMA control method

Publications (2)

Publication Number Publication Date
JPS56121131A true JPS56121131A (en) 1981-09-22
JPS5932814B2 JPS5932814B2 (en) 1984-08-11

Family

ID=12142500

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2459580A Expired JPS5932814B2 (en) 1980-02-28 1980-02-28 DMA control method

Country Status (1)

Country Link
JP (1) JPS5932814B2 (en)

Also Published As

Publication number Publication date
JPS5932814B2 (en) 1984-08-11

Similar Documents

Publication Publication Date Title
KR900007680B1 (en) Input/output control system
JPS57113162A (en) High-speed external storage device
JPS55143635A (en) Input-output controller
JPS56121131A (en) Dma control system
ES8106062A1 (en) Digital information transfer system and interface.
JPS5436140A (en) Control unit for magnetic disc
JPS578829A (en) Input and output controller
JPS55154623A (en) Input and output control system
JPS573126A (en) Input and output controlling system
JPS5638631A (en) Data transfer apparatus
JPS57200985A (en) Buffer memory device
JPS55108030A (en) Data transfer control system
JPS5733472A (en) Memory access control system
JPS5616256A (en) Disc cash system
JPS57176471A (en) Information processing system
JPS5694425A (en) Receiving data transfer control system
JPS569826A (en) Channel controller
JPS52136533A (en) Byte alignment system
JPS5498134A (en) Input/output control system
JPS55112661A (en) Memory control unit
JPS5659337A (en) Data processing system
JPS57117052A (en) Address controller
JPS54153541A (en) Control system for interruption priority
JPS5498135A (en) Input/output control system
JPS54124644A (en) Data transfer system