JPS56121120A - Setting method for initial state of information processor - Google Patents

Setting method for initial state of information processor

Info

Publication number
JPS56121120A
JPS56121120A JP2481780A JP2481780A JPS56121120A JP S56121120 A JPS56121120 A JP S56121120A JP 2481780 A JP2481780 A JP 2481780A JP 2481780 A JP2481780 A JP 2481780A JP S56121120 A JPS56121120 A JP S56121120A
Authority
JP
Japan
Prior art keywords
reset signal
reset
signal
initial state
setting method
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2481780A
Other languages
Japanese (ja)
Inventor
Toshinori Otsuka
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP2481780A priority Critical patent/JPS56121120A/en
Publication of JPS56121120A publication Critical patent/JPS56121120A/en
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/24—Resetting means

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)

Abstract

PURPOSE:To reset an internal circuit having a memory function without requiring an inverter, by providing a reset signal generating circuit which generates a reset signal in response to either value of a binary signal. CONSTITUTION:Between reset signal line 1 and internal circuits 6-9 with the memory function, reset signal processing circuit 13 is connected which receives two kinds of detection signals generated by detecting the variation of a binary signal between two values and then generates a reset signal for resetting internal circuits 6-9 at the post stage. Therefore, even when the reset signal from signal line 1 has either value, internal circuits 6-9 can be reset without any inverter which converts the reset signal.
JP2481780A 1980-02-28 1980-02-28 Setting method for initial state of information processor Pending JPS56121120A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2481780A JPS56121120A (en) 1980-02-28 1980-02-28 Setting method for initial state of information processor

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2481780A JPS56121120A (en) 1980-02-28 1980-02-28 Setting method for initial state of information processor

Publications (1)

Publication Number Publication Date
JPS56121120A true JPS56121120A (en) 1981-09-22

Family

ID=12148734

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2481780A Pending JPS56121120A (en) 1980-02-28 1980-02-28 Setting method for initial state of information processor

Country Status (1)

Country Link
JP (1) JPS56121120A (en)

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS53109428A (en) * 1977-03-07 1978-09-25 Toshiba Corp Automatic clear circuit system

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS53109428A (en) * 1977-03-07 1978-09-25 Toshiba Corp Automatic clear circuit system

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