JPS56117384A - Cash controller - Google Patents

Cash controller

Info

Publication number
JPS56117384A
JPS56117384A JP2010980A JP2010980A JPS56117384A JP S56117384 A JPS56117384 A JP S56117384A JP 2010980 A JP2010980 A JP 2010980A JP 2010980 A JP2010980 A JP 2010980A JP S56117384 A JPS56117384 A JP S56117384A
Authority
JP
Japan
Prior art keywords
address
word
stacker
processing
bit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2010980A
Other languages
Japanese (ja)
Inventor
Hiroshi Oota
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP2010980A priority Critical patent/JPS56117384A/en
Publication of JPS56117384A publication Critical patent/JPS56117384A/en
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0844—Multiple simultaneous or quasi-simultaneous cache accessing
    • G06F12/0855—Overlapped cache accessing, e.g. pipeline
    • G06F12/0859—Overlapped cache accessing, e.g. pipeline with reload from main memory

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Memory System Of A Hierarchy Structure (AREA)

Abstract

PURPOSE:To reduce the processing time, by adding the display bit during data transfer to the address array and providing the address word/address stacker of pushup store. CONSTITUTION:To address array 2, in addition to the effectiveness display bit V, the bit T displaying that the readout request data is under transferring from the main memory device is added. Further, the column address word address stacker 7 of FIFO system storing the column address and word address, and the comparator 9 are provided. Further, by controlling these at the control section 5, a plurality of processing requests from the processor are sequentially received for parallel processing, resulting that the waiting time is decreased and the processing time can be reduced.
JP2010980A 1980-02-20 1980-02-20 Cash controller Pending JPS56117384A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2010980A JPS56117384A (en) 1980-02-20 1980-02-20 Cash controller

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2010980A JPS56117384A (en) 1980-02-20 1980-02-20 Cash controller

Publications (1)

Publication Number Publication Date
JPS56117384A true JPS56117384A (en) 1981-09-14

Family

ID=12017946

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2010980A Pending JPS56117384A (en) 1980-02-20 1980-02-20 Cash controller

Country Status (1)

Country Link
JP (1) JPS56117384A (en)

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS58214946A (en) * 1982-06-08 1983-12-14 Nec Corp Controlling system of microprogram
JPS62118456A (en) * 1985-11-19 1987-05-29 Nec Corp Cache memory
JPH0210446A (en) * 1988-06-28 1990-01-16 Hitachi Ltd Buffer storage device
JP2002351850A (en) * 2001-03-22 2002-12-06 Sony Computer Entertainment Inc Data processing method on processor and data processing system
JP2005100034A (en) * 2003-09-24 2005-04-14 Matsushita Electric Ind Co Ltd Information processing control system
JP2010033480A (en) * 2008-07-31 2010-02-12 Sony Corp Cache memory and cache memory control apparatus

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS58214946A (en) * 1982-06-08 1983-12-14 Nec Corp Controlling system of microprogram
JPS62118456A (en) * 1985-11-19 1987-05-29 Nec Corp Cache memory
JPH0210446A (en) * 1988-06-28 1990-01-16 Hitachi Ltd Buffer storage device
JP2002351850A (en) * 2001-03-22 2002-12-06 Sony Computer Entertainment Inc Data processing method on processor and data processing system
JP2005100034A (en) * 2003-09-24 2005-04-14 Matsushita Electric Ind Co Ltd Information processing control system
US8135909B2 (en) 2003-09-24 2012-03-13 Panasonic Corporation System for starting a preload of a second program while a first program is executing
JP2010033480A (en) * 2008-07-31 2010-02-12 Sony Corp Cache memory and cache memory control apparatus

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