JPS56112117A - Delay circuit - Google Patents

Delay circuit

Info

Publication number
JPS56112117A
JPS56112117A JP1577980A JP1577980A JPS56112117A JP S56112117 A JPS56112117 A JP S56112117A JP 1577980 A JP1577980 A JP 1577980A JP 1577980 A JP1577980 A JP 1577980A JP S56112117 A JPS56112117 A JP S56112117A
Authority
JP
Japan
Prior art keywords
becomes
constant
delay time
gamma0
temperature
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP1577980A
Other languages
Japanese (ja)
Inventor
Toshitaka Tsuda
Kazuo Murano
Takafumi Nakajo
Norio Murakami
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP1577980A priority Critical patent/JPS56112117A/en
Publication of JPS56112117A publication Critical patent/JPS56112117A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K5/13—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals

Landscapes

  • Physics & Mathematics (AREA)
  • Nonlinear Science (AREA)
  • Pulse Circuits (AREA)
  • Electronic Switches (AREA)

Abstract

PURPOSE:To make delay time constant by varying the electrice power source of the gate for delay, in accordance with the temperature coefficient of the resistance. CONSTITUTION:The output voltage of the operational amplifier OP has the temperature characteristic when the input voltage Vr is constant, and is becomes V(T)= Vr[1+R4.(1+KT)/R5]. The delay time consisting of the gate circuit GT becomes gamma(T, V)=gamma0(1+K0T-K1T). In this case, when K1, K.R4/R5 K0 is made by selecting Vr and R4/R5, the delay time becomes gamma(T, V) gamma0, and it becomes an almost constant dely time against changes of temperature.
JP1577980A 1980-02-12 1980-02-12 Delay circuit Pending JPS56112117A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1577980A JPS56112117A (en) 1980-02-12 1980-02-12 Delay circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1577980A JPS56112117A (en) 1980-02-12 1980-02-12 Delay circuit

Publications (1)

Publication Number Publication Date
JPS56112117A true JPS56112117A (en) 1981-09-04

Family

ID=11898293

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1577980A Pending JPS56112117A (en) 1980-02-12 1980-02-12 Delay circuit

Country Status (1)

Country Link
JP (1) JPS56112117A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6297421A (en) * 1986-08-12 1987-05-06 Nippon Gakki Seizo Kk Pulse fm detection circuit

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6297421A (en) * 1986-08-12 1987-05-06 Nippon Gakki Seizo Kk Pulse fm detection circuit
JPH0261169B2 (en) * 1986-08-12 1990-12-19 Yamaha Corp

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