JPS56111184A - Control system of memory system - Google Patents

Control system of memory system

Info

Publication number
JPS56111184A
JPS56111184A JP1447280A JP1447280A JPS56111184A JP S56111184 A JPS56111184 A JP S56111184A JP 1447280 A JP1447280 A JP 1447280A JP 1447280 A JP1447280 A JP 1447280A JP S56111184 A JPS56111184 A JP S56111184A
Authority
JP
Japan
Prior art keywords
refresh
memory
ram10
fed
decrease
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP1447280A
Other languages
Japanese (ja)
Inventor
Kiyohiko Kobayashi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Ricoh Co Ltd
Original Assignee
Ricoh Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Ricoh Co Ltd filed Critical Ricoh Co Ltd
Priority to JP1447280A priority Critical patent/JPS56111184A/en
Publication of JPS56111184A publication Critical patent/JPS56111184A/en
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/24—Memory cell safety or protection circuits, e.g. arrangements for preventing inadvertent reading or writing; Status cells; Test cells

Abstract

PURPOSE:To prevent malfuction and to operate the system stably, by inhibiting read-in and writeout and read-in access through the decrease in the supplied power voltage to a cell type dynamic RAM and making continuous refresh. CONSTITUTION:When the decrease in the power supply voltage is detected at a comparator 1, an FF3 for request is set and a refresh cycle FF5 is set in synchronizing with the end period of the memory cycle immediately before in response to the timing signal from a processing system 8 with a synchronizing circuit 4. When the set output of the FF5 is fed, the access to a conventional RAM10 from the system 8 is inhibited, and the AND gate is controlled and the load address strobe 23 for refresh from a refresh timing generator 7 is fed to the address of the RAM10 designated with the refresh counter 6 to make continuous refresh. Accordingly, the memory content is kept without malfunction even at lowering in the power supply voltage and the memory system can stably be operated.
JP1447280A 1980-02-07 1980-02-07 Control system of memory system Pending JPS56111184A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1447280A JPS56111184A (en) 1980-02-07 1980-02-07 Control system of memory system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1447280A JPS56111184A (en) 1980-02-07 1980-02-07 Control system of memory system

Publications (1)

Publication Number Publication Date
JPS56111184A true JPS56111184A (en) 1981-09-02

Family

ID=11861994

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1447280A Pending JPS56111184A (en) 1980-02-07 1980-02-07 Control system of memory system

Country Status (1)

Country Link
JP (1) JPS56111184A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60225968A (en) * 1984-04-25 1985-11-11 Seiko Epson Corp Electronic computer
JPS6173299A (en) * 1984-09-19 1986-04-15 Hitachi Ltd Semiconductor memory device
JPS61271694A (en) * 1985-05-27 1986-12-01 Mitsubishi Electric Corp Memory device

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60225968A (en) * 1984-04-25 1985-11-11 Seiko Epson Corp Electronic computer
JPS6173299A (en) * 1984-09-19 1986-04-15 Hitachi Ltd Semiconductor memory device
JPS61271694A (en) * 1985-05-27 1986-12-01 Mitsubishi Electric Corp Memory device

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