JPS56110237A - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JPS56110237A
JPS56110237A JP1248180A JP1248180A JPS56110237A JP S56110237 A JPS56110237 A JP S56110237A JP 1248180 A JP1248180 A JP 1248180A JP 1248180 A JP1248180 A JP 1248180A JP S56110237 A JPS56110237 A JP S56110237A
Authority
JP
Japan
Prior art keywords
type
groove
depth
substrate
glass
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP1248180A
Other languages
Japanese (ja)
Other versions
JPS6214939B2 (en
Inventor
Toshiki Kurosu
Masatami Miura
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP1248180A priority Critical patent/JPS56110237A/en
Publication of JPS56110237A publication Critical patent/JPS56110237A/en
Publication of JPS6214939B2 publication Critical patent/JPS6214939B2/ja
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Thyristors (AREA)
  • Formation Of Insulating Films (AREA)

Abstract

PURPOSE:To prevent high-temperature leak current and cracking of a substrate by providing a groove so that a P-N junction part may be exposed and making the depth of the groove 70-110% of the P-N junction depth by means of a glass passivation semiconductor element to be coated with a glass flim. CONSTITUTION:A glass passivation thyrister pellet 1 is composed of a P type emitter diffusion layer 6, an N type substrate 5, a P type base diffusion layer 4 and an N type emitter diffusion layer 3. An exposed P-N junction part between the N type substrate 5 and the P type emitter layer 6 as well as the said part between the N type substrate 5 and the P type base layer 4 has a groove formed respectively. Then the groove is coated by a glass. The depth of the groove (z) is equivalent to 70-110% of the depth of the P-N junction xjp . Thus a high-temperature leak current can be minimized and the cracking of a semiconductor substrate at time of assembly can be prevented.
JP1248180A 1980-02-06 1980-02-06 Semiconductor device Granted JPS56110237A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1248180A JPS56110237A (en) 1980-02-06 1980-02-06 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1248180A JPS56110237A (en) 1980-02-06 1980-02-06 Semiconductor device

Publications (2)

Publication Number Publication Date
JPS56110237A true JPS56110237A (en) 1981-09-01
JPS6214939B2 JPS6214939B2 (en) 1987-04-04

Family

ID=11806577

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1248180A Granted JPS56110237A (en) 1980-02-06 1980-02-06 Semiconductor device

Country Status (1)

Country Link
JP (1) JPS56110237A (en)

Also Published As

Publication number Publication date
JPS6214939B2 (en) 1987-04-04

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