JPS56105678A - Field-effect transistor - Google Patents

Field-effect transistor

Info

Publication number
JPS56105678A
JPS56105678A JP898280A JP898280A JPS56105678A JP S56105678 A JPS56105678 A JP S56105678A JP 898280 A JP898280 A JP 898280A JP 898280 A JP898280 A JP 898280A JP S56105678 A JPS56105678 A JP S56105678A
Authority
JP
Japan
Prior art keywords
layer
substrate
concave sections
source electrode
electrode
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP898280A
Other languages
Japanese (ja)
Inventor
Manabu Watase
Michihiro Kobiki
Yasuro Mitsui
Mutsuyuki Otsubo
Takashi Ishii
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP898280A priority Critical patent/JPS56105678A/en
Publication of JPS56105678A publication Critical patent/JPS56105678A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76Unipolar devices, e.g. field effect transistors
    • H01L29/772Field effect transistors
    • H01L29/80Field effect transistors with field effect produced by a PN or other rectifying junction gate, i.e. potential-jump barrier
    • H01L29/812Field effect transistors with field effect produced by a PN or other rectifying junction gate, i.e. potential-jump barrier with a Schottky gate

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Junction Field-Effect Transistors (AREA)

Abstract

PURPOSE:To increase areas which a drain electrode and a source electrode oppose to drain currents and decrease current concentration by a method wherein an active semiconductor layer is formed to one section on a semi-insulating substrate, and the drain electrode and the source electrode are each made up over a surface of the substrate from the two opposing end surfaces of the substrate and the layer. CONSTITUTION:A GaAs semiconductor layer 2, an active layer, is formed on a semi-insulating GaAs substrate 1 by means of gaseous phase epitaxial growth method etc., and concave sections 8, 9 having the desired patterns, which reach the substrate 1, are selectively made up by means of an ion milling method holding the layer 2 remaining between the concave sections. In this case, the inclinations of the inwall surfaces of the concave sections 8, 9 to a surface of the layer 2 are previously made fixed values by selecting a milling condition. The surfaces of the concave sections 8, 9 are covered with a drain electrode 3a and a source electrode 4a in Au, Ge, etc., a Schottky electrode 5 in Al, etc. is formed on the layer 2 and the concave sections are separately cut according to an X-Y line and a Y-Y line. Thus, the deterioration of breakdown resistance is inhibited, and parasitic capacity is further lowered.
JP898280A 1980-01-28 1980-01-28 Field-effect transistor Pending JPS56105678A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP898280A JPS56105678A (en) 1980-01-28 1980-01-28 Field-effect transistor

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP898280A JPS56105678A (en) 1980-01-28 1980-01-28 Field-effect transistor

Publications (1)

Publication Number Publication Date
JPS56105678A true JPS56105678A (en) 1981-08-22

Family

ID=11707888

Family Applications (1)

Application Number Title Priority Date Filing Date
JP898280A Pending JPS56105678A (en) 1980-01-28 1980-01-28 Field-effect transistor

Country Status (1)

Country Link
JP (1) JPS56105678A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2005129696A (en) * 2003-10-23 2005-05-19 Matsushita Electric Ind Co Ltd Semiconductor device and its manufacturing method

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS52109375A (en) * 1976-03-10 1977-09-13 Nec Corp Manufacture of junction gate type field effect transistor

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS52109375A (en) * 1976-03-10 1977-09-13 Nec Corp Manufacture of junction gate type field effect transistor

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2005129696A (en) * 2003-10-23 2005-05-19 Matsushita Electric Ind Co Ltd Semiconductor device and its manufacturing method

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