JPS56105539A - Adder of pcm signal - Google Patents

Adder of pcm signal

Info

Publication number
JPS56105539A
JPS56105539A JP774380A JP774380A JPS56105539A JP S56105539 A JPS56105539 A JP S56105539A JP 774380 A JP774380 A JP 774380A JP 774380 A JP774380 A JP 774380A JP S56105539 A JPS56105539 A JP S56105539A
Authority
JP
Japan
Prior art keywords
values
subtractor
adder
bit
absolute value
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP774380A
Other languages
Japanese (ja)
Inventor
Yasushi Wakahara
Yoshikazu Ikeda
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
KDDI Corp
Original Assignee
Kokusai Denshin Denwa KK
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Kokusai Denshin Denwa KK filed Critical Kokusai Denshin Denwa KK
Priority to JP774380A priority Critical patent/JPS56105539A/en
Priority to GB8030171A priority patent/GB2059123B/en
Priority to US06/189,539 priority patent/US4357674A/en
Publication of JPS56105539A publication Critical patent/JPS56105539A/en
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G06F7/49—Computations with a radix, other than binary, 8, 16 or decimal, e.g. ternary, negative or imaginary radices, mixed radix non-linear PCM
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04B—TRANSMISSION
    • H04B14/00—Transmission systems not characterised by the medium used for transmission
    • H04B14/02—Transmission systems not characterised by the medium used for transmission characterised by the use of pulse modulation
    • H04B14/04—Transmission systems not characterised by the medium used for transmission characterised by the use of pulse modulation using pulse code modulation
    • H04B14/046—Systems or methods for reducing noise or bandwidth
    • H04B14/048—Non linear compression or expansion
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04M—TELEPHONIC COMMUNICATION
    • H04M3/00—Automatic or semi-automatic exchanges
    • H04M3/42—Systems providing special services or facilities to subscribers
    • H04M3/56—Arrangements for connecting several subscribers to a common circuit, i.e. affording conference facilities
    • H04M3/561—Arrangements for connecting several subscribers to a common circuit, i.e. affording conference facilities by multiplexing

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Signal Processing (AREA)
  • Computational Mathematics (AREA)
  • Computing Systems (AREA)
  • Mathematical Analysis (AREA)
  • Mathematical Optimization (AREA)
  • Nonlinear Science (AREA)
  • Pure & Applied Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Multimedia (AREA)
  • General Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)

Abstract

PURPOSE:To make possible high-speed operation with a small circuit scale by making digit matching of step values in SG according to the difference in the segment SG values of PCM signals and making predetermined calculations with two adders. CONSTITUTION:The bit components of SG values out of the absolute value of the input PCM signals from terminals 10, 11 are applied to a subtractor 30 and OR circuits 39, 40, and the bit components of the remaining step values are applied to shift registers SRs 35, 36. The subtractor 30 applies the absolute value of the differences in the SG values to a pulse generator 31, and applies the bit showing the magnitude of the SG values to a gate 34 and to a gate 33 via an inverter 32. When the input absolute value from the terminal 10 is larger than that from the terminal 11, the pulses from the generator 31 are applied to the SR36, so that it is shifted in the direction of lowering digits by the number of said pulses. In a converse case, the SR35 is shifted. The outputs of the SRs 35, 36 are inputted to an adder 37, by which they are added in such a state that they are converted to a linear signal, and if the overflowed bit is 1, this information is applied to an adder 38, by which it is added to the information from the subtractor 30, whereby the correct SG value is obtained.
JP774380A 1979-09-22 1980-01-28 Adder of pcm signal Pending JPS56105539A (en)

Priority Applications (3)

Application Number Priority Date Filing Date Title
JP774380A JPS56105539A (en) 1980-01-28 1980-01-28 Adder of pcm signal
GB8030171A GB2059123B (en) 1979-09-22 1980-09-18 Pcm signal calculator
US06/189,539 US4357674A (en) 1979-09-22 1980-09-22 PCM Signal calculator

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP774380A JPS56105539A (en) 1980-01-28 1980-01-28 Adder of pcm signal

Publications (1)

Publication Number Publication Date
JPS56105539A true JPS56105539A (en) 1981-08-22

Family

ID=11674176

Family Applications (1)

Application Number Title Priority Date Filing Date
JP774380A Pending JPS56105539A (en) 1979-09-22 1980-01-28 Adder of pcm signal

Country Status (1)

Country Link
JP (1) JPS56105539A (en)

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS54158830A (en) * 1978-06-06 1979-12-15 Fujitsu Ltd High-speed arithmetic processing system

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS54158830A (en) * 1978-06-06 1979-12-15 Fujitsu Ltd High-speed arithmetic processing system

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