JPS56103736A - Bidirectional code converter - Google Patents
Bidirectional code converterInfo
- Publication number
- JPS56103736A JPS56103736A JP495580A JP495580A JPS56103736A JP S56103736 A JPS56103736 A JP S56103736A JP 495580 A JP495580 A JP 495580A JP 495580 A JP495580 A JP 495580A JP S56103736 A JPS56103736 A JP S56103736A
- Authority
- JP
- Japan
- Prior art keywords
- signal
- circuit
- addition
- binary
- pure
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M7/00—Conversion of a code where information is represented by a given sequence or number of digits to a code where the same, similar or subset of information is represented by a different sequence or number of digits
- H03M7/02—Conversion to or from weighted codes, i.e. the weight given to a digit depending on the position of the digit within the block or code word
- H03M7/12—Conversion to or from weighted codes, i.e. the weight given to a digit depending on the position of the digit within the block or code word having two radices, e.g. binary-coded-decimal code
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Dc Digital Transmission (AREA)
Abstract
PURPOSE:To make bidirectional code conversion for binary coded decimal signal and pure binary signal with a simple circuit constitution, by constituting the bidirectional code conversion circuit with a gate circuit and an addition circuit outputting an addition signal of + or - depending on the content of an input signal. CONSTITUTION:An input signal 1 by binary coded decimal signal or pure binary signal is fed to a gate circuit 3 and an addition circuit 5, and a gate signal 2 indicating the input signal whether it is a decimal signal or a pure binary signal, is fed to the gate circuit 3. This gate circuit 3 outputs an addition signal 4 of + or - according to the content of input signal, this addition signal 4 is fed to the addition circuit 5, the addition circuit 5 outputs the lowest figure of the input signal 1 as it is, and the rest signal and the addition signal 4 are added by assuming it to a pure binary signal, and the pure binary signal or binary coded decimal signal being the output signal is output as an output signal 6. Further, with a simple circuit constitution, the bidirectional code conversion between the binary coded decimal signal and the pure binary signal are made possible.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP495580A JPS56103736A (en) | 1980-01-18 | 1980-01-18 | Bidirectional code converter |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP495580A JPS56103736A (en) | 1980-01-18 | 1980-01-18 | Bidirectional code converter |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS56103736A true JPS56103736A (en) | 1981-08-19 |
Family
ID=11597991
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP495580A Pending JPS56103736A (en) | 1980-01-18 | 1980-01-18 | Bidirectional code converter |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS56103736A (en) |
-
1980
- 1980-01-18 JP JP495580A patent/JPS56103736A/en active Pending
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