JPS56103554A - Parallel-serial-parallel data converter - Google Patents
Parallel-serial-parallel data converterInfo
- Publication number
- JPS56103554A JPS56103554A JP538980A JP538980A JPS56103554A JP S56103554 A JPS56103554 A JP S56103554A JP 538980 A JP538980 A JP 538980A JP 538980 A JP538980 A JP 538980A JP S56103554 A JPS56103554 A JP S56103554A
- Authority
- JP
- Japan
- Prior art keywords
- parallel
- counter
- clock signal
- serial
- data
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L25/00—Baseband systems
- H04L25/38—Synchronous or start-stop systems, e.g. for Baudot code
- H04L25/40—Transmitting circuits; Receiving circuits
- H04L25/45—Transmitting circuits; Receiving circuits using electronic distributors
Landscapes
- Engineering & Computer Science (AREA)
- Computer Networks & Wireless Communication (AREA)
- Signal Processing (AREA)
- Time-Division Multiplex Systems (AREA)
- Dc Digital Transmission (AREA)
- Synchronisation In Digital Transmission Systems (AREA)
Abstract
PURPOSE:To realize a highly efficient transmission/reception of data, by securing a synchronism through a simple constitution for each sampling signal during the parallel/serial and serial/parallel data conversions. CONSTITUTION:The D-FF15 divides the reference clock signal SCK1 into two parts to deliver the clock signal CK1 of 25Hz frequency through the output terminal Q. The D-FF45 divides the reference clock signal SCK2 into two parts to deliver the clock signal CK2 of 25Hz frequency through the output terminal Q'. The 1st and 2nd counters 16 and 46 count the pulse numbers of the signals SCK1 and SCK2 and then generate the sampling output signals for conversion of data while switching the output terminals successively according to the count number. The counter 46 starts counting by the start of counter 16 to give a compensation to the delay of operation for the counter 46 to the counter 16.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP538980A JPS56103554A (en) | 1980-01-21 | 1980-01-21 | Parallel-serial-parallel data converter |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP538980A JPS56103554A (en) | 1980-01-21 | 1980-01-21 | Parallel-serial-parallel data converter |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS56103554A true JPS56103554A (en) | 1981-08-18 |
Family
ID=11609800
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP538980A Pending JPS56103554A (en) | 1980-01-21 | 1980-01-21 | Parallel-serial-parallel data converter |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS56103554A (en) |
Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS495513A (en) * | 1972-05-02 | 1974-01-18 | ||
JPS4947230A (en) * | 1972-04-22 | 1974-05-07 | ||
JPS5020586B1 (en) * | 1970-10-30 | 1975-07-16 | ||
JPS54156360A (en) * | 1978-05-31 | 1979-12-10 | Matsushita Electric Works Ltd | Step dimming system |
-
1980
- 1980-01-21 JP JP538980A patent/JPS56103554A/en active Pending
Patent Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5020586B1 (en) * | 1970-10-30 | 1975-07-16 | ||
JPS4947230A (en) * | 1972-04-22 | 1974-05-07 | ||
JPS495513A (en) * | 1972-05-02 | 1974-01-18 | ||
JPS54156360A (en) * | 1978-05-31 | 1979-12-10 | Matsushita Electric Works Ltd | Step dimming system |
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