JPS5593242A - Structure for mounting clock circuit - Google Patents

Structure for mounting clock circuit

Info

Publication number
JPS5593242A
JPS5593242A JP62279A JP62279A JPS5593242A JP S5593242 A JPS5593242 A JP S5593242A JP 62279 A JP62279 A JP 62279A JP 62279 A JP62279 A JP 62279A JP S5593242 A JPS5593242 A JP S5593242A
Authority
JP
Japan
Prior art keywords
crystal
chip
thereafter
sealed
capacity
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP62279A
Other languages
Japanese (ja)
Other versions
JPS6129543B2 (en
Inventor
Kazuo Inoue
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Citizen Watch Co Ltd
Original Assignee
Citizen Watch Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Citizen Watch Co Ltd filed Critical Citizen Watch Co Ltd
Priority to JP62279A priority Critical patent/JPS5593242A/en
Publication of JPS5593242A publication Critical patent/JPS5593242A/en
Publication of JPS6129543B2 publication Critical patent/JPS6129543B2/ja
Granted legal-status Critical Current

Links

Landscapes

  • Electric Clocks (AREA)
  • Electromechanical Clocks (AREA)
  • Structures For Mounting Electric Components On Printed Circuit Boards (AREA)

Abstract

PURPOSE: To reduce the parts number and the process by a method wherein the frame coupling and the mold material are sealed while at the same time the crystal vibrator and the capacity are decided to be positioned, thus, being made to operate as a vibration buffer crystal supporting seat.
CONSTITUTION: The circuit pattern 2 is formed on the circuit substrate 1, and the coupling area 2a and the solder bumper electrode 3 of the IC chip 3 are coupled. Thereafter, the thermoplastic bonding material sheet 10 of the specified shape is mounted on the specified position and it is heated to melt under the appropriate condition and then, the chip 3 is sealed. At the same time, the crystal oscillator 7 and the capacity 8, etc. are bound at the specified position and then, they are cooled and fixed. Thereafter, the circuit connection is performed. In this structure, the process is simplified, therefore, the process number is reduced and the yield is improved. Furthermore, the number of parts such as the mold frame and the stopper of crystal, etc. is reduced and the structure is permitted to be made small and thin.
COPYRIGHT: (C)1980,JPO&Japio
JP62279A 1979-01-10 1979-01-10 Structure for mounting clock circuit Granted JPS5593242A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP62279A JPS5593242A (en) 1979-01-10 1979-01-10 Structure for mounting clock circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP62279A JPS5593242A (en) 1979-01-10 1979-01-10 Structure for mounting clock circuit

Publications (2)

Publication Number Publication Date
JPS5593242A true JPS5593242A (en) 1980-07-15
JPS6129543B2 JPS6129543B2 (en) 1986-07-07

Family

ID=11478820

Family Applications (1)

Application Number Title Priority Date Filing Date
JP62279A Granted JPS5593242A (en) 1979-01-10 1979-01-10 Structure for mounting clock circuit

Country Status (1)

Country Link
JP (1) JPS5593242A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS58182456U (en) * 1982-05-31 1983-12-05 日本電気株式会社 hybrid integrated circuit
CN103716981A (en) * 2013-12-30 2014-04-09 惠州Tcl家电集团有限公司 PCB for stabilizing clock signals and wiring method for PCB

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS58182456U (en) * 1982-05-31 1983-12-05 日本電気株式会社 hybrid integrated circuit
CN103716981A (en) * 2013-12-30 2014-04-09 惠州Tcl家电集团有限公司 PCB for stabilizing clock signals and wiring method for PCB

Also Published As

Publication number Publication date
JPS6129543B2 (en) 1986-07-07

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