JPS5592071A - Copying unit - Google Patents

Copying unit

Info

Publication number
JPS5592071A
JPS5592071A JP16518878A JP16518878A JPS5592071A JP S5592071 A JPS5592071 A JP S5592071A JP 16518878 A JP16518878 A JP 16518878A JP 16518878 A JP16518878 A JP 16518878A JP S5592071 A JPS5592071 A JP S5592071A
Authority
JP
Japan
Prior art keywords
circuit
read
code
group
comparator
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP16518878A
Other languages
Japanese (ja)
Other versions
JPS6150546B2 (en
Inventor
Shinji Miura
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Ricoh Co Ltd
Original Assignee
Ricoh Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Ricoh Co Ltd filed Critical Ricoh Co Ltd
Priority to JP16518878A priority Critical patent/JPS5592071A/en
Publication of JPS5592071A publication Critical patent/JPS5592071A/en
Publication of JPS6150546B2 publication Critical patent/JPS6150546B2/ja
Granted legal-status Critical Current

Links

Abstract

PURPOSE: To make a recording speed high by skipping the read of picture information, which is not recorded, to reduce waste of the read time.
CONSTITUTION: In respect to line sensor 1, plural photoelectric conversion elements are divided into m-number groups, and an output end and a drive end are provided for every group, and two-phase transfer clock pulses are inputted to the drive end. Read selection circuit 2 is constituted by MOSFET F1∼F2m and decoder 2a, and a code indicating a group is inputted from group selection circuit 3 to this circuit 2. Circuit 3 is constituted by OR gate OR1, AND gate AND1, AND gate AND2, counter 3a and comparator 3b, and a code indicating a read width is inputted from read width setting circuit 4 to this circuit 3. Circuit 4 is constituted by start and terminal address buffers 4a and 4b and gives the start group code of buffer 4a and the terminal code of buffer 4b to counter 3a and comparator 3b respectively. When the code of counter 3a becomes equal to the code of buffer 4b, comparator 3b generates an output of high level "1" to indicate the end of read of one-line components.
COPYRIGHT: (C)1980,JPO&Japio
JP16518878A 1978-12-30 1978-12-30 Copying unit Granted JPS5592071A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP16518878A JPS5592071A (en) 1978-12-30 1978-12-30 Copying unit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP16518878A JPS5592071A (en) 1978-12-30 1978-12-30 Copying unit

Publications (2)

Publication Number Publication Date
JPS5592071A true JPS5592071A (en) 1980-07-12
JPS6150546B2 JPS6150546B2 (en) 1986-11-05

Family

ID=15807502

Family Applications (1)

Application Number Title Priority Date Filing Date
JP16518878A Granted JPS5592071A (en) 1978-12-30 1978-12-30 Copying unit

Country Status (1)

Country Link
JP (1) JPS5592071A (en)

Also Published As

Publication number Publication date
JPS6150546B2 (en) 1986-11-05

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