JPS5591836A - Manufacture of electronic device - Google Patents

Manufacture of electronic device

Info

Publication number
JPS5591836A
JPS5591836A JP16397578A JP16397578A JPS5591836A JP S5591836 A JPS5591836 A JP S5591836A JP 16397578 A JP16397578 A JP 16397578A JP 16397578 A JP16397578 A JP 16397578A JP S5591836 A JPS5591836 A JP S5591836A
Authority
JP
Japan
Prior art keywords
mold
electrode
substrate
keeping
semiconductor element
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP16397578A
Other languages
Japanese (ja)
Inventor
Masami Umetsu
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Seiko Epson Corp
Suwa Seikosha KK
Original Assignee
Seiko Epson Corp
Suwa Seikosha KK
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Seiko Epson Corp, Suwa Seikosha KK filed Critical Seiko Epson Corp
Priority to JP16397578A priority Critical patent/JPS5591836A/en
Publication of JPS5591836A publication Critical patent/JPS5591836A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93Batch processes
    • H01L24/95Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/96Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being encapsulated in a common layer, e.g. neo-wafer or pseudo-wafer, said common layer being separable into individual assemblies after connecting

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Wire Bonding (AREA)

Abstract

PURPOSE:To eliminate the formation of step in level between surfaces of an electronic part and a substrate, by placing a substrate-making dielectric material into a mold in such a position as to cover surrounding of an electric part placed in the forming mold keeping the electrode with its surface on the bottom side and hardening it by applying pressure or heat. CONSTITUTION:In a cavity 5a of a bottom mold 5 for forming a dielectiric substrate 2, a semiconductor element 1 is placed by keeping its electrode 1a dwnward, and by applying pressure and heat onto the top by a plunger 6a of a top mold 6, a product is obtained. The dielectric materials 2a are to consist of phenol, diallylphthalate and ceramic, etc., and the preformed materials may be used. Since it is possible in this manner to proceed with forming operation while keeping the semiconductor element 1's electrode 1a pressed against a flat surface in the cavity 5a of the bottom mold 5, the semiconductor element 1 can be formed keeping surfaces of the electrode 1a and the substrate 2 on the same level, and therefore, breakage in wiring works to be done later can be eliminated.
JP16397578A 1978-12-29 1978-12-29 Manufacture of electronic device Pending JPS5591836A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP16397578A JPS5591836A (en) 1978-12-29 1978-12-29 Manufacture of electronic device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP16397578A JPS5591836A (en) 1978-12-29 1978-12-29 Manufacture of electronic device

Publications (1)

Publication Number Publication Date
JPS5591836A true JPS5591836A (en) 1980-07-11

Family

ID=15784366

Family Applications (1)

Application Number Title Priority Date Filing Date
JP16397578A Pending JPS5591836A (en) 1978-12-29 1978-12-29 Manufacture of electronic device

Country Status (1)

Country Link
JP (1) JPS5591836A (en)

Similar Documents

Publication Publication Date Title
SE7509025L (en) CONTACT DEVICE FOR AN ELECTRIC CONDUCTIVE PLATE FOREMAL AND PROCEDURE FOR MANUFACTURE OF CONTACT DEVICES.
JPS5591836A (en) Manufacture of electronic device
JPS57178149A (en) Manufacture of electric heater
JPS6472546A (en) Semiconductor device
JPS5632749A (en) Manufacture of semiconductor device
JPS5737839A (en) Manufacture of hybrid integrated circuit
JPS5591839A (en) Production of electronic parts
JPS5591837A (en) Manufacture of electronic device
JPS54114790A (en) Conductive coupling of metal and metal foil
JPS55130134A (en) Bonding method of semiconductor pellet
JPS6461923A (en) Surface mounting for semiconductor element
JPS5374367A (en) Semiconductor device
JPS54107264A (en) Semiconductor device
JPS5521175A (en) Semiconductor device
JPS57100026A (en) Manufacture of interior material
JPS572537A (en) Semiconductor device
JPS6442843A (en) Semiconductor device
JPS55103747A (en) Manufacture of semiconductor device
JPS54131872A (en) Forming method for dielectric layer of semiconductor device
JPS5311816B2 (en)
JPS54149468A (en) Production of resin seal-type semiconductor device
JPS55107252A (en) Manufacture of semiconductor device
JPS5743435A (en) Electronic part
JPS5775452A (en) Mos capacitor in semiconductor integrated circuit and manufacture thereof
JPS57121256A (en) Ceramic multilayer wiring structure