JPS5591836A - Manufacture of electronic device - Google Patents
Manufacture of electronic deviceInfo
- Publication number
- JPS5591836A JPS5591836A JP16397578A JP16397578A JPS5591836A JP S5591836 A JPS5591836 A JP S5591836A JP 16397578 A JP16397578 A JP 16397578A JP 16397578 A JP16397578 A JP 16397578A JP S5591836 A JPS5591836 A JP S5591836A
- Authority
- JP
- Japan
- Prior art keywords
- mold
- electrode
- substrate
- keeping
- semiconductor element
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/93—Batch processes
- H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L24/96—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being encapsulated in a common layer, e.g. neo-wafer or pseudo-wafer, said common layer being separable into individual assemblies after connecting
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Wire Bonding (AREA)
Abstract
PURPOSE:To eliminate the formation of step in level between surfaces of an electronic part and a substrate, by placing a substrate-making dielectric material into a mold in such a position as to cover surrounding of an electric part placed in the forming mold keeping the electrode with its surface on the bottom side and hardening it by applying pressure or heat. CONSTITUTION:In a cavity 5a of a bottom mold 5 for forming a dielectiric substrate 2, a semiconductor element 1 is placed by keeping its electrode 1a dwnward, and by applying pressure and heat onto the top by a plunger 6a of a top mold 6, a product is obtained. The dielectric materials 2a are to consist of phenol, diallylphthalate and ceramic, etc., and the preformed materials may be used. Since it is possible in this manner to proceed with forming operation while keeping the semiconductor element 1's electrode 1a pressed against a flat surface in the cavity 5a of the bottom mold 5, the semiconductor element 1 can be formed keeping surfaces of the electrode 1a and the substrate 2 on the same level, and therefore, breakage in wiring works to be done later can be eliminated.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP16397578A JPS5591836A (en) | 1978-12-29 | 1978-12-29 | Manufacture of electronic device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP16397578A JPS5591836A (en) | 1978-12-29 | 1978-12-29 | Manufacture of electronic device |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS5591836A true JPS5591836A (en) | 1980-07-11 |
Family
ID=15784366
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP16397578A Pending JPS5591836A (en) | 1978-12-29 | 1978-12-29 | Manufacture of electronic device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS5591836A (en) |
-
1978
- 1978-12-29 JP JP16397578A patent/JPS5591836A/en active Pending
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