JPS5590866A - Function testing machine for digital integrated circuit - Google Patents

Function testing machine for digital integrated circuit

Info

Publication number
JPS5590866A
JPS5590866A JP16506378A JP16506378A JPS5590866A JP S5590866 A JPS5590866 A JP S5590866A JP 16506378 A JP16506378 A JP 16506378A JP 16506378 A JP16506378 A JP 16506378A JP S5590866 A JPS5590866 A JP S5590866A
Authority
JP
Japan
Prior art keywords
outputs
supplied
pattern
integrated circuit
testing machine
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP16506378A
Other languages
Japanese (ja)
Other versions
JPS5950944B2 (en
Inventor
Hiroshi Tsukada
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP53165063A priority Critical patent/JPS5950944B2/en
Publication of JPS5590866A publication Critical patent/JPS5590866A/en
Publication of JPS5950944B2 publication Critical patent/JPS5950944B2/en
Expired legal-status Critical Current

Links

Landscapes

  • Testing Or Measuring Of Semiconductors Or The Like (AREA)
  • Tests Of Electronic Circuits (AREA)

Abstract

PURPOSE: To carry out complete test by detecting abnormality in comparison of outputs of a standard device or a device to be tested at every time where the output of any of both devices varies.
CONSTITUTION: A test pattern from a pattern generator 1 is supplied to a standard device 4 and a device 5 to be tested. Level comparators 6 and 7 receive the outputs of devices 4 and 5, and the outputs are delivered to a pattern comparator 10. Further, the outputs are supplied through delay circuits 8 and 9 to a pattern comparator 10, and further supplied to one-shot multipliers 11 and 12 to produce strove pulses. The outputs of level comparators 6 and 7 are coincident with each other, if they are normal, and they are not coincident, if they are abnormal. As a result, the output state of a good or bad signal generator 13 is varied.
COPYRIGHT: (C)1980,JPO&Japio
JP53165063A 1978-12-29 1978-12-29 Digital integrated circuit function tester Expired JPS5950944B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP53165063A JPS5950944B2 (en) 1978-12-29 1978-12-29 Digital integrated circuit function tester

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP53165063A JPS5950944B2 (en) 1978-12-29 1978-12-29 Digital integrated circuit function tester

Publications (2)

Publication Number Publication Date
JPS5590866A true JPS5590866A (en) 1980-07-09
JPS5950944B2 JPS5950944B2 (en) 1984-12-11

Family

ID=15805143

Family Applications (1)

Application Number Title Priority Date Filing Date
JP53165063A Expired JPS5950944B2 (en) 1978-12-29 1978-12-29 Digital integrated circuit function tester

Country Status (1)

Country Link
JP (1) JPS5950944B2 (en)

Also Published As

Publication number Publication date
JPS5950944B2 (en) 1984-12-11

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