JPS5588459A - Signal demodulation circuit - Google Patents
Signal demodulation circuitInfo
- Publication number
- JPS5588459A JPS5588459A JP16401378A JP16401378A JPS5588459A JP S5588459 A JPS5588459 A JP S5588459A JP 16401378 A JP16401378 A JP 16401378A JP 16401378 A JP16401378 A JP 16401378A JP S5588459 A JPS5588459 A JP S5588459A
- Authority
- JP
- Japan
- Prior art keywords
- circuit
- signal
- pll
- regeneration period
- action
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Abstract
PURPOSE: To always ensure the high-accuracy regeneration of the signal information by securing the sufficient follow-up for the AGC and PLL actions at the signal demodulation circuit to the necessary signals.
CONSTITUTION: The envelope curve detection output which gave the answer to regeneration signal sig sequentially is fed back to variable gain amplifier circuit 10 from peak detection holding circuit 20 in the data region regeneration period during which sector signal sec is "0", thus featuring the normal AGC action. When signal sec changed from "0"∼"1" with start of the servo region regeneration period, circuit 20 is cut off. And thus the immediately preceding envelope curve detection output is fed back to circuit 10 to be fixed to the constant gain. In the same way as the AGC circuit, the oscillation frequency of variable frequency oscillator 40 is fixed to the fixed line in the PLL circuit for the servo region regeneration period via the action of holding circuit 70. Thus the PLL action can be restarted smoothly even when the data region regeneration period is secured.
COPYRIGHT: (C)1980,JPO&Japio
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP16401378A JPS5588459A (en) | 1978-12-25 | 1978-12-25 | Signal demodulation circuit |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP16401378A JPS5588459A (en) | 1978-12-25 | 1978-12-25 | Signal demodulation circuit |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS5588459A true JPS5588459A (en) | 1980-07-04 |
Family
ID=15785110
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP16401378A Pending JPS5588459A (en) | 1978-12-25 | 1978-12-25 | Signal demodulation circuit |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS5588459A (en) |
Cited By (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5812459A (en) * | 1981-07-15 | 1983-01-24 | Hitachi Ltd | Modem training control system |
JPS6180668A (en) * | 1984-09-28 | 1986-04-24 | Nec Corp | Automatic gain control circuit |
JPS62241112A (en) * | 1986-04-14 | 1987-10-21 | Mitsubishi Electric Corp | Reproducing device |
JPS62198732U (en) * | 1986-06-07 | 1987-12-17 | ||
JPS6425371A (en) * | 1987-07-22 | 1989-01-27 | Sony Corp | Magnetic disk device |
JPH0795056A (en) * | 1993-05-10 | 1995-04-07 | Internatl Business Mach Corp <Ibm> | Variable frequency standard clock formation device |
-
1978
- 1978-12-25 JP JP16401378A patent/JPS5588459A/en active Pending
Cited By (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5812459A (en) * | 1981-07-15 | 1983-01-24 | Hitachi Ltd | Modem training control system |
JPS6180668A (en) * | 1984-09-28 | 1986-04-24 | Nec Corp | Automatic gain control circuit |
JPH0560187B2 (en) * | 1984-09-28 | 1993-09-01 | Nippon Electric Co | |
JPS62241112A (en) * | 1986-04-14 | 1987-10-21 | Mitsubishi Electric Corp | Reproducing device |
JPS62198732U (en) * | 1986-06-07 | 1987-12-17 | ||
JPS6425371A (en) * | 1987-07-22 | 1989-01-27 | Sony Corp | Magnetic disk device |
JPH0795056A (en) * | 1993-05-10 | 1995-04-07 | Internatl Business Mach Corp <Ibm> | Variable frequency standard clock formation device |
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