JPS5588412A - Expansion circuit - Google Patents

Expansion circuit

Info

Publication number
JPS5588412A
JPS5588412A JP16247278A JP16247278A JPS5588412A JP S5588412 A JPS5588412 A JP S5588412A JP 16247278 A JP16247278 A JP 16247278A JP 16247278 A JP16247278 A JP 16247278A JP S5588412 A JPS5588412 A JP S5588412A
Authority
JP
Japan
Prior art keywords
circuit
potential
expansion circuit
capacitor
turned
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP16247278A
Other languages
Japanese (ja)
Inventor
Masashige Sone
Satoshi Arai
Nobuaki Hori
Nobuhiro Okamoto
Masaji Miyachi
Takashi Wakakuri
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Japan Broadcasting Corp
Original Assignee
NEC Corp
Nippon Hoso Kyokai NHK
Nippon Electric Co Ltd
Japan Broadcasting Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Hoso Kyokai NHK, Nippon Electric Co Ltd, Japan Broadcasting Corp filed Critical NEC Corp
Priority to JP16247278A priority Critical patent/JPS5588412A/en
Publication of JPS5588412A publication Critical patent/JPS5588412A/en
Pending legal-status Critical Current

Links

Landscapes

  • Tone Control, Compression And Expansion, Limiting Amplitude (AREA)

Abstract

PURPOSE: To reduce the ripple for the expansion circuit using the multiplication circuit by delaying the discharge of the capacitor in the rectifier/smoothing circuit of the input signal.
CONSTITUTION: With decrement of input signal (a), the charging ends for capacitor C1. However, the potential can be kept constant at point (d) since transistor TR1 is off. Subtraction circuit 4 uses the difference voltage between points (d) and (e) as output (b), and thus the potential increases gradually at point (c). When this potential exceeds the reference voltage of comparator 5, TR1 is turned on via comparator 5 to charge C1. And if the minimum frequency supplied to the expansion circuit is set to fmin and thus time T during which TR1 is turned on is set more than double the minimum frequency, the DC ripple component supplied to multiplication circuit 1 can be eliminated practically.
COPYRIGHT: (C)1980,JPO&Japio
JP16247278A 1978-12-26 1978-12-26 Expansion circuit Pending JPS5588412A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP16247278A JPS5588412A (en) 1978-12-26 1978-12-26 Expansion circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP16247278A JPS5588412A (en) 1978-12-26 1978-12-26 Expansion circuit

Publications (1)

Publication Number Publication Date
JPS5588412A true JPS5588412A (en) 1980-07-04

Family

ID=15755267

Family Applications (1)

Application Number Title Priority Date Filing Date
JP16247278A Pending JPS5588412A (en) 1978-12-26 1978-12-26 Expansion circuit

Country Status (1)

Country Link
JP (1) JPS5588412A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5756023U (en) * 1980-09-18 1982-04-01

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5756023U (en) * 1980-09-18 1982-04-01

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