JPS5585148A - Side peak reduction circuit - Google Patents
Side peak reduction circuitInfo
- Publication number
- JPS5585148A JPS5585148A JP15979878A JP15979878A JPS5585148A JP S5585148 A JPS5585148 A JP S5585148A JP 15979878 A JP15979878 A JP 15979878A JP 15979878 A JP15979878 A JP 15979878A JP S5585148 A JPS5585148 A JP S5585148A
- Authority
- JP
- Japan
- Prior art keywords
- side peak
- detector
- output
- rejected
- fed
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04B—TRANSMISSION
- H04B1/00—Details of transmission systems, not covered by a single one of groups H04B3/00 - H04B13/00; Details of transmission systems not characterised by the medium used for transmission
- H04B1/06—Receivers
- H04B1/10—Means associated with receiver for limiting or suppressing noise or interference
Landscapes
- Engineering & Computer Science (AREA)
- Computer Networks & Wireless Communication (AREA)
- Signal Processing (AREA)
- Noise Elimination (AREA)
Abstract
PURPOSE:To attenuate the side peak in FM reception, by using the output voltage of level and S curve from the intermediate frequency amplifying section. CONSTITUTION:The S curve output of the quadrature detector 3 is fed to the Tr32, 33 of differential amplifier via the bidirectional switching transistors Tr9, 10 to drive them. The audio output of the detector 3 is fed to electronic volume consisting of Tr13-23 and outputted from the output terminal 24. The side peak is rejected by leaving around 0dB at the both ends with the switching of Tr30, 31 of differential amplifier. The remaining side peak is detected with the detector 5 for the level change for each stage of the intermediate frequncy amplifier 2 and is rejected by feeding the level change detection voltage to the base of Tr34 via Tr35.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP15979878A JPS5585148A (en) | 1978-12-21 | 1978-12-21 | Side peak reduction circuit |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP15979878A JPS5585148A (en) | 1978-12-21 | 1978-12-21 | Side peak reduction circuit |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS5585148A true JPS5585148A (en) | 1980-06-26 |
JPS6311812B2 JPS6311812B2 (en) | 1988-03-16 |
Family
ID=15701484
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP15979878A Granted JPS5585148A (en) | 1978-12-21 | 1978-12-21 | Side peak reduction circuit |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS5585148A (en) |
Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS54157017A (en) * | 1978-05-31 | 1979-12-11 | Nec Corp | Fm signal receiving circuit |
-
1978
- 1978-12-21 JP JP15979878A patent/JPS5585148A/en active Granted
Patent Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS54157017A (en) * | 1978-05-31 | 1979-12-11 | Nec Corp | Fm signal receiving circuit |
Also Published As
Publication number | Publication date |
---|---|
JPS6311812B2 (en) | 1988-03-16 |
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