JPS56110311A - Amplifying circuit - Google Patents

Amplifying circuit

Info

Publication number
JPS56110311A
JPS56110311A JP1262280A JP1262280A JPS56110311A JP S56110311 A JPS56110311 A JP S56110311A JP 1262280 A JP1262280 A JP 1262280A JP 1262280 A JP1262280 A JP 1262280A JP S56110311 A JPS56110311 A JP S56110311A
Authority
JP
Japan
Prior art keywords
fets
amplifying circuit
terms
terminal
component
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP1262280A
Other languages
Japanese (ja)
Other versions
JPS6110B2 (en
Inventor
Tomoyori Shimabukuro
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Victor Company of Japan Ltd
Original Assignee
Victor Company of Japan Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Victor Company of Japan Ltd filed Critical Victor Company of Japan Ltd
Priority to JP1262280A priority Critical patent/JPS56110311A/en
Publication of JPS56110311A publication Critical patent/JPS56110311A/en
Publication of JPS6110B2 publication Critical patent/JPS6110B2/ja
Granted legal-status Critical Current

Links

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  • Amplifiers (AREA)

Abstract

PURPOSE: To realize an amplification with a high S/N, by forming several units of FET into a complementary differential amplifying circuit in terms of DC and also securing a parallel connection among those FETs in terms of AC respectively.
CONSTITUTION: The input signal supplied to the terminal 1 is applied to the FETs Q1 and Q2. The AC component of the input signal is applied to the FETs Q3 and Q4 via the capacitor C1 and accordingly amplified by a parallel circuit of FETs Q1∼Q4 to increase the S/N. On the other hand, the DC component of the output signal delivered through the terminal 2 is fed back to the gate of the FETs Q3 and Q4 via the resistance R14. Thus the DC gain of the amplifying circuit can be set to 0, and the quality of sound can be improved in case when the acoustic signal is used for the input.
COPYRIGHT: (C)1981,JPO&Japio
JP1262280A 1980-02-05 1980-02-05 Amplifying circuit Granted JPS56110311A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1262280A JPS56110311A (en) 1980-02-05 1980-02-05 Amplifying circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1262280A JPS56110311A (en) 1980-02-05 1980-02-05 Amplifying circuit

Publications (2)

Publication Number Publication Date
JPS56110311A true JPS56110311A (en) 1981-09-01
JPS6110B2 JPS6110B2 (en) 1986-01-06

Family

ID=11810468

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1262280A Granted JPS56110311A (en) 1980-02-05 1980-02-05 Amplifying circuit

Country Status (1)

Country Link
JP (1) JPS56110311A (en)

Also Published As

Publication number Publication date
JPS6110B2 (en) 1986-01-06

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