JPS5585058A - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JPS5585058A
JPS5585058A JP15737778A JP15737778A JPS5585058A JP S5585058 A JPS5585058 A JP S5585058A JP 15737778 A JP15737778 A JP 15737778A JP 15737778 A JP15737778 A JP 15737778A JP S5585058 A JPS5585058 A JP S5585058A
Authority
JP
Japan
Prior art keywords
upper electrode
semiconductor
contacts
compression
semiconductor device
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP15737778A
Other languages
Japanese (ja)
Inventor
Takashi Namekawa
Keiichi Kuniya
Hideo Arakawa
Hiroshi Miyata
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP15737778A priority Critical patent/JPS5585058A/en
Publication of JPS5585058A publication Critical patent/JPS5585058A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/2612—Auxiliary members for layer connectors, e.g. spacers

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Die Bonding (AREA)

Abstract

PURPOSE: To prevent generation of excessive compression pressure near an outer circumferencial portion of an upper electrode, by a method wherein upper and lower electrodes are each mounted to both sides of a semiconductor substrate of a compression type semiconductor device, and the end portions of a surface at the side where the upper electrode contacts with a semiconductor are rounded.
CONSTITUTION: A compression type semiconductor device is formed in such a manner that discoid upper electrode 1 and lower electrode 2 are attached onto the both sides of an orbicular semiconductor 4 with solder 3. When applying compression pressure to the upper and lower electrodes, compression stress is produced on the whole surface of a surface where the semiconductor contacts with the upper electrode, but excessive compression stress is particularly generated to an outer circumferential portion of the upper electrode concentrically. Since the compression stress is lightened by rounding the end portion 1a of the surface where the upper electrode 1 contacts with the semiconductor 4, the breakage and cracks of the semiconductor can be prevented. It is preferable that the upper electrode is manufactured by copper or a copper alloy with excellent heat and electric conductivity to which carbon fibers are buried.
COPYRIGHT: (C)1980,JPO&Japio
JP15737778A 1978-12-22 1978-12-22 Semiconductor device Pending JPS5585058A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP15737778A JPS5585058A (en) 1978-12-22 1978-12-22 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP15737778A JPS5585058A (en) 1978-12-22 1978-12-22 Semiconductor device

Publications (1)

Publication Number Publication Date
JPS5585058A true JPS5585058A (en) 1980-06-26

Family

ID=15648321

Family Applications (1)

Application Number Title Priority Date Filing Date
JP15737778A Pending JPS5585058A (en) 1978-12-22 1978-12-22 Semiconductor device

Country Status (1)

Country Link
JP (1) JPS5585058A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63120448A (en) * 1986-11-08 1988-05-24 Matsushita Electric Works Ltd Substrate for heat dissipation
US5374494A (en) * 1991-03-13 1994-12-20 Canon Kabushiki Kaisha Electrophotographic photosensitive member, electrophotographic apparatus, device unit, and facsimile machine employing the same

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63120448A (en) * 1986-11-08 1988-05-24 Matsushita Electric Works Ltd Substrate for heat dissipation
US5374494A (en) * 1991-03-13 1994-12-20 Canon Kabushiki Kaisha Electrophotographic photosensitive member, electrophotographic apparatus, device unit, and facsimile machine employing the same

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