JPS558065A - Lead wire cutting moulding machine - Google Patents

Lead wire cutting moulding machine

Info

Publication number
JPS558065A
JPS558065A JP8089078A JP8089078A JPS558065A JP S558065 A JPS558065 A JP S558065A JP 8089078 A JP8089078 A JP 8089078A JP 8089078 A JP8089078 A JP 8089078A JP S558065 A JPS558065 A JP S558065A
Authority
JP
Japan
Prior art keywords
frame
lead wire
cutters
slid
cut
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP8089078A
Other languages
English (en)
Japanese (ja)
Other versions
JPS6156622B2 (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html
Inventor
Mikio Itamochi
Shigetaka Takahashi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Akita Electronics Systems Co Ltd
Original Assignee
Hitachi Ltd
Akita Electronics Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd, Akita Electronics Co Ltd filed Critical Hitachi Ltd
Priority to JP8089078A priority Critical patent/JPS558065A/ja
Publication of JPS558065A publication Critical patent/JPS558065A/ja
Publication of JPS6156622B2 publication Critical patent/JPS6156622B2/ja
Granted legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item

Landscapes

  • Lead Frames For Integrated Circuits (AREA)
JP8089078A 1978-07-05 1978-07-05 Lead wire cutting moulding machine Granted JPS558065A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP8089078A JPS558065A (en) 1978-07-05 1978-07-05 Lead wire cutting moulding machine

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP8089078A JPS558065A (en) 1978-07-05 1978-07-05 Lead wire cutting moulding machine

Publications (2)

Publication Number Publication Date
JPS558065A true JPS558065A (en) 1980-01-21
JPS6156622B2 JPS6156622B2 (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html) 1986-12-03

Family

ID=13730939

Family Applications (1)

Application Number Title Priority Date Filing Date
JP8089078A Granted JPS558065A (en) 1978-07-05 1978-07-05 Lead wire cutting moulding machine

Country Status (1)

Country Link
JP (1) JPS558065A (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH02109601U (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html) * 1989-02-17 1990-09-03

Also Published As

Publication number Publication date
JPS6156622B2 (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html) 1986-12-03

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