JPS558053A - Semiconductor and manufacture thereof - Google Patents

Semiconductor and manufacture thereof

Info

Publication number
JPS558053A
JPS558053A JP8034878A JP8034878A JPS558053A JP S558053 A JPS558053 A JP S558053A JP 8034878 A JP8034878 A JP 8034878A JP 8034878 A JP8034878 A JP 8034878A JP S558053 A JPS558053 A JP S558053A
Authority
JP
Japan
Prior art keywords
base
range
emitter
film
pads
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP8034878A
Other languages
Japanese (ja)
Inventor
Kimihiro Hanya
Makoto Shimanuki
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP8034878A priority Critical patent/JPS558053A/en
Publication of JPS558053A publication Critical patent/JPS558053A/en
Pending legal-status Critical Current

Links

Landscapes

  • Electrodes Of Semiconductors (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Formation Of Insulating Films (AREA)

Abstract

PURPOSE: For effectively preventing the passage of water, gas and ions, to use a laminate film made of glass coat and the silicon varnish coat provided thereon when forming protective film on an element range and the metallic wiring to be connected thereto.
CONSTITUTION: A base range 4 and an inside emitter range 5 are diffusedly formed with SiO2 film 3 used as mask in the Si substrate 1 which forms a corrector range. Base and emitter electrode metallic wirings 6 and 7 are deposited on said ranges 4 and 5. Next, glass coat 8 is provided on the portions from which bonding pads 61 and 71 are removed, of said electrodes, and a corrector conductor 2 is fastened on the reverse side of said substrate 1. Thereafter, one end of base and emitter inside wirings 10 and 9 is connected to said pads 61 and 71, and the other to not- illustrated emitter and base conductors. Thereafter, Silicon varnish coat 11 is provided on a film 8 and said pads 61 and 71 to protect transistors sufficiently.
COPYRIGHT: (C)1980,JPO&Japio
JP8034878A 1978-06-30 1978-06-30 Semiconductor and manufacture thereof Pending JPS558053A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP8034878A JPS558053A (en) 1978-06-30 1978-06-30 Semiconductor and manufacture thereof

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP8034878A JPS558053A (en) 1978-06-30 1978-06-30 Semiconductor and manufacture thereof

Publications (1)

Publication Number Publication Date
JPS558053A true JPS558053A (en) 1980-01-21

Family

ID=13715744

Family Applications (1)

Application Number Title Priority Date Filing Date
JP8034878A Pending JPS558053A (en) 1978-06-30 1978-06-30 Semiconductor and manufacture thereof

Country Status (1)

Country Link
JP (1) JPS558053A (en)

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