JPS5580171A - Pattern coding and decoding processing system - Google Patents

Pattern coding and decoding processing system

Info

Publication number
JPS5580171A
JPS5580171A JP15399778A JP15399778A JPS5580171A JP S5580171 A JPS5580171 A JP S5580171A JP 15399778 A JP15399778 A JP 15399778A JP 15399778 A JP15399778 A JP 15399778A JP S5580171 A JPS5580171 A JP S5580171A
Authority
JP
Japan
Prior art keywords
pattern
memory
run
circuit
data
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP15399778A
Other languages
Japanese (ja)
Other versions
JPS5840774B2 (en
Inventor
Yasuhito Suenaga
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Nippon Telegraph and Telephone Corp
Original Assignee
Nippon Telegraph and Telephone Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nippon Telegraph and Telephone Corp filed Critical Nippon Telegraph and Telephone Corp
Priority to JP15399778A priority Critical patent/JPS5840774B2/en
Publication of JPS5580171A publication Critical patent/JPS5580171A/en
Publication of JPS5840774B2 publication Critical patent/JPS5840774B2/en
Expired legal-status Critical Current

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  • Image Processing (AREA)

Abstract

PURPOSE:To make it possible to express a pattern with a smaller amount of data by dividing pattern information into data of pattern components of a form and a small number of attribute data and coding them and reproducing the pattern by giving attributes to respective pattern components. CONSTITUTION:The first run length code r1 is read out from memory 209 by read circuit 202 and is decoded by decoder circuit 201 and is sent to buffer memory 203 and linkage decision circuit 204. When deciding that this run r1 is the first run, circuit 204 sends a signal to read circuit 205. Circuit 205 reads out the first color data c2 in memory 210 and stores it in memory 203 in a pair of it and run r1. Pattern signal generation circuit 207 reads out one-line components of run r1 and data c1 from memory 203 and converts them to pattern signals and outputs them to pattern output device 208. Continuously, runs r2, r3... are read out from memory 209 successively, and color data in memory 210 are read out successively and caused to correspond to runs only when peak runs appear, and the same color as the preceding-line linking run is given to other runs.
JP15399778A 1978-12-12 1978-12-12 Graphic encoding and decoding processing method Expired JPS5840774B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP15399778A JPS5840774B2 (en) 1978-12-12 1978-12-12 Graphic encoding and decoding processing method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP15399778A JPS5840774B2 (en) 1978-12-12 1978-12-12 Graphic encoding and decoding processing method

Publications (2)

Publication Number Publication Date
JPS5580171A true JPS5580171A (en) 1980-06-17
JPS5840774B2 JPS5840774B2 (en) 1983-09-07

Family

ID=15574649

Family Applications (1)

Application Number Title Priority Date Filing Date
JP15399778A Expired JPS5840774B2 (en) 1978-12-12 1978-12-12 Graphic encoding and decoding processing method

Country Status (1)

Country Link
JP (1) JPS5840774B2 (en)

Also Published As

Publication number Publication date
JPS5840774B2 (en) 1983-09-07

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