JPS5579522A - Receiver - Google Patents

Receiver

Info

Publication number
JPS5579522A
JPS5579522A JP15390678A JP15390678A JPS5579522A JP S5579522 A JPS5579522 A JP S5579522A JP 15390678 A JP15390678 A JP 15390678A JP 15390678 A JP15390678 A JP 15390678A JP S5579522 A JPS5579522 A JP S5579522A
Authority
JP
Japan
Prior art keywords
terminal
divider
level
inputted
switches
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP15390678A
Other languages
Japanese (ja)
Inventor
Jiro Kitanaka
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Priority to JP15390678A priority Critical patent/JPS5579522A/en
Publication of JPS5579522A publication Critical patent/JPS5579522A/en
Pending legal-status Critical Current

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Landscapes

  • Channel Selection Circuits, Automatic Tuning Circuits (AREA)

Abstract

PURPOSE: To attain automatic rapid channel selection by varying the division ratio of a programmable divider by fixed steps only in the operation of the programmable divider.
CONSTITUTION: Once broadcasting is received, detector 6 develops a voltage of level "1", which is inputted to terminal 2 of programmable divider 1 to stop the counter of divider 1. Switches S1 and S2 interlock each other and turning the both ON inputs level "1" to terminal 3 of divider 1, thereby starting counter operation. With switches S1 and S2 OFF next, an input signal to terminal 3 is differentiated into negative pulses, which are inputted to reset terminal (r) of FF circuit 8. Output Q of FF8 is set to level "1" by negative pulses to terminal (r) and clock input T inverts an output at a rise of an input of level "1". Then, switches S1 and S2 turn ON afterward and when no broadcasting is received at this time, output C of AND gate 10 is held at "1" by outputs of inverter 9 and FF8 and then inputted to terminal 4 of divider 1 so as to vary the division ratio by fixed steps, so that rapid channel selection will be done.
COPYRIGHT: (C)1980,JPO&Japio
JP15390678A 1978-12-12 1978-12-12 Receiver Pending JPS5579522A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP15390678A JPS5579522A (en) 1978-12-12 1978-12-12 Receiver

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP15390678A JPS5579522A (en) 1978-12-12 1978-12-12 Receiver

Publications (1)

Publication Number Publication Date
JPS5579522A true JPS5579522A (en) 1980-06-16

Family

ID=15572683

Family Applications (1)

Application Number Title Priority Date Filing Date
JP15390678A Pending JPS5579522A (en) 1978-12-12 1978-12-12 Receiver

Country Status (1)

Country Link
JP (1) JPS5579522A (en)

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