JPS5573108A - Fm signal demodulator - Google Patents

Fm signal demodulator

Info

Publication number
JPS5573108A
JPS5573108A JP14662378A JP14662378A JPS5573108A JP S5573108 A JPS5573108 A JP S5573108A JP 14662378 A JP14662378 A JP 14662378A JP 14662378 A JP14662378 A JP 14662378A JP S5573108 A JPS5573108 A JP S5573108A
Authority
JP
Japan
Prior art keywords
output
oscillator
delivered
counter
led
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP14662378A
Other languages
Japanese (ja)
Inventor
Makoto Nakamura
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Tokyo Shibaura Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp, Tokyo Shibaura Electric Co Ltd filed Critical Toshiba Corp
Priority to JP14662378A priority Critical patent/JPS5573108A/en
Publication of JPS5573108A publication Critical patent/JPS5573108A/en
Pending legal-status Critical Current

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Abstract

PURPOSE: To enhance the temperature characteristics by measuring the length of one cycle of the input FM signal through counting of the clocks supplied from the high- speed oscillator and then reading the output signals from the memory which memorized them previously and in accordance with the number of the clocks.
CONSTITUTION: The digital signals sent from the limiter at the control signal demodulation part of the lincompex communication equipment are supplied to counter 31. Then the mean value is delivered to be led to detection circuit 32, and single pulse 302 is delivered to be supplied to latch 35. At the same time, counter 34 is cleared via pulse 303 which is rather delayed. Then high-speed oscillator 33 is connected to counter 34 to transfer the number of the high-speed clocks equivalent to one cycle of latch 35. The output of latck 35 is led to the address of ROM35, and the output value corresponding to the input frequency value memorized previously is delivered to be then led to D/A converter 37 for output of the analog signals. Oscillator 33 is a fixed oscillator comprising the memory and the digital circuit, thus obtaining easily an FM demodulator circuit which excels in the temperature characteristics and the reliability.
COPYRIGHT: (C)1980,JPO&Japio
JP14662378A 1978-11-29 1978-11-29 Fm signal demodulator Pending JPS5573108A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP14662378A JPS5573108A (en) 1978-11-29 1978-11-29 Fm signal demodulator

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP14662378A JPS5573108A (en) 1978-11-29 1978-11-29 Fm signal demodulator

Publications (1)

Publication Number Publication Date
JPS5573108A true JPS5573108A (en) 1980-06-02

Family

ID=15411914

Family Applications (1)

Application Number Title Priority Date Filing Date
JP14662378A Pending JPS5573108A (en) 1978-11-29 1978-11-29 Fm signal demodulator

Country Status (1)

Country Link
JP (1) JPS5573108A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62163405A (en) * 1986-01-13 1987-07-20 Ayao Miura Demodulator of frequency modulation wave

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62163405A (en) * 1986-01-13 1987-07-20 Ayao Miura Demodulator of frequency modulation wave

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