JPS5572257A - Integrated circuit - Google Patents

Integrated circuit

Info

Publication number
JPS5572257A
JPS5572257A JP14619978A JP14619978A JPS5572257A JP S5572257 A JPS5572257 A JP S5572257A JP 14619978 A JP14619978 A JP 14619978A JP 14619978 A JP14619978 A JP 14619978A JP S5572257 A JPS5572257 A JP S5572257A
Authority
JP
Japan
Prior art keywords
ffs
same substrate
signal
terminals
outputted
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP14619978A
Other languages
Japanese (ja)
Inventor
Haruo Yano
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP14619978A priority Critical patent/JPS5572257A/en
Publication of JPS5572257A publication Critical patent/JPS5572257A/en
Pending legal-status Critical Current

Links

Landscapes

  • Semiconductor Integrated Circuits (AREA)
  • Testing Or Measuring Of Semiconductors Or The Like (AREA)
  • Test And Diagnosis Of Digital Computers (AREA)

Abstract

PURPOSE: To make it possible to form on the same substrate hysteresis registers corresponding to FFs by constituting respective terminals on the same substrate including a test-result output terminal where a signal obtained from final-stage FF in a group of FF is outputted.
CONSTITUTION: External input terminals 12...18 receive external signals and then store them in one FF7. A signal from this FF7 is outputted from normal output terminals 19 and 20 and clock input terminal 18 receives an external arrival clock signal. Further, FFs 8...11, connected so that sequential shifts are made in response to a clock from terminal 18 on reception of a signal from FF7, are constituted on the same substrate including a test-result output terminal where a signal obtained from final-stage FF11 among FFs 8...11 is outputted. Consequently, hysteresis registers corresponding to FFs can be formed on the same substrate without increasing external terminals in number.
COPYRIGHT: (C)1980,JPO&Japio
JP14619978A 1978-11-27 1978-11-27 Integrated circuit Pending JPS5572257A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP14619978A JPS5572257A (en) 1978-11-27 1978-11-27 Integrated circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP14619978A JPS5572257A (en) 1978-11-27 1978-11-27 Integrated circuit

Publications (1)

Publication Number Publication Date
JPS5572257A true JPS5572257A (en) 1980-05-30

Family

ID=15402360

Family Applications (1)

Application Number Title Priority Date Filing Date
JP14619978A Pending JPS5572257A (en) 1978-11-27 1978-11-27 Integrated circuit

Country Status (1)

Country Link
JP (1) JPS5572257A (en)

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS4985939A (en) * 1972-12-22 1974-08-17
JPS51135339A (en) * 1975-05-20 1976-11-24 Fujitsu Ltd Hysteresis holding control system in a logical equipment
JPS5237740A (en) * 1975-09-20 1977-03-23 Fujitsu Ltd Logging system for computer system

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS4985939A (en) * 1972-12-22 1974-08-17
JPS51135339A (en) * 1975-05-20 1976-11-24 Fujitsu Ltd Hysteresis holding control system in a logical equipment
JPS5237740A (en) * 1975-09-20 1977-03-23 Fujitsu Ltd Logging system for computer system

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