JPS5572226A - Address control circuit - Google Patents

Address control circuit

Info

Publication number
JPS5572226A
JPS5572226A JP14460278A JP14460278A JPS5572226A JP S5572226 A JPS5572226 A JP S5572226A JP 14460278 A JP14460278 A JP 14460278A JP 14460278 A JP14460278 A JP 14460278A JP S5572226 A JPS5572226 A JP S5572226A
Authority
JP
Japan
Prior art keywords
address buses
address
boundary
bus
registers
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP14460278A
Other languages
Japanese (ja)
Other versions
JPS5852258B2 (en
Inventor
Mitsuo Terajima
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Tokyo Shibaura Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp, Tokyo Shibaura Electric Co Ltd filed Critical Toshiba Corp
Priority to JP53144602A priority Critical patent/JPS5852258B2/en
Publication of JPS5572226A publication Critical patent/JPS5572226A/en
Publication of JPS5852258B2 publication Critical patent/JPS5852258B2/en
Expired legal-status Critical Current

Links

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  • Executing Machine-Instructions (AREA)
  • Debugging And Monitoring (AREA)

Abstract

PURPOSE: To simplify bus control differing in the number of address buses by easily setting a boundary between address buses by controlling bus addresses by a microprogram, by cascading address registers with connected address buses.
CONSTITUTION: Carry output terminal CA and borrow output terminal BR of the lowest-order register 91 of cascaded address registers 91W9n are connected to those of post-stage register 92 respectively. After the completion of the execution of microprogram instructions in access to a bus, access to a boundary of address buses is attained and operation code OP is decoded by decoding circuit 6; and an instruction to count up the bus addresses by +1 or -1 is sent out and a carry or borrow signal is supplied to registers 91W9n. Then, the output of register 9n is fed back by OR circuits 7 and 8 to prevent addresses from forming a loop, thereby generating easily the boundary of address buses.
COPYRIGHT: (C)1980,JPO&Japio
JP53144602A 1978-11-22 1978-11-22 address control circuit Expired JPS5852258B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP53144602A JPS5852258B2 (en) 1978-11-22 1978-11-22 address control circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP53144602A JPS5852258B2 (en) 1978-11-22 1978-11-22 address control circuit

Publications (2)

Publication Number Publication Date
JPS5572226A true JPS5572226A (en) 1980-05-30
JPS5852258B2 JPS5852258B2 (en) 1983-11-21

Family

ID=15365843

Family Applications (1)

Application Number Title Priority Date Filing Date
JP53144602A Expired JPS5852258B2 (en) 1978-11-22 1978-11-22 address control circuit

Country Status (1)

Country Link
JP (1) JPS5852258B2 (en)

Also Published As

Publication number Publication date
JPS5852258B2 (en) 1983-11-21

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