JPS55677A - Analog input device - Google Patents

Analog input device

Info

Publication number
JPS55677A
JPS55677A JP715379A JP715379A JPS55677A JP S55677 A JPS55677 A JP S55677A JP 715379 A JP715379 A JP 715379A JP 715379 A JP715379 A JP 715379A JP S55677 A JPS55677 A JP S55677A
Authority
JP
Japan
Prior art keywords
power supply
resistance
input
capacitor
filter
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP715379A
Other languages
Japanese (ja)
Inventor
Ikuyasu Horinaka
Tatsuo Matsuida
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP715379A priority Critical patent/JPS55677A/en
Publication of JPS55677A publication Critical patent/JPS55677A/en
Pending legal-status Critical Current

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Abstract

PURPOSE: To reduce the effect of the transformer sag and thus to increase the accuracy of the compensation circuit by increasing the input impedance regardless of On or OFF of the power supply of the device.
CONSTITUTION: Resistance 2 of the input filter and capacitor 3 or resistance 1 of the input filter are connected in series via the source and the drain of FET 12 by making use of the fact that the enhancement type of MOSFET12 is turned off at the non-bias time. The power supply of the device is connected to gate terminal 2, and FET12 is switched on when the power supply is ON to transmit the input signal voltage to filter capacitor 3. While FET12 is switched off when the power supply is OFF, with the input signal voltage cut off. Thus, the input resistance is increased greatly when viewed from the signal source, and at the same time junction type FET19 featuring a comparatively low ON-resistance is provided between capacitor 3 and transformer 5 to perform switching. Then the waveform featuring the reduced amount of sag is transmitted to the secondary side to ensure the high- accuracy insulated transmission.
COPYRIGHT: (C)1980,JPO&Japio
JP715379A 1979-01-26 1979-01-26 Analog input device Pending JPS55677A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP715379A JPS55677A (en) 1979-01-26 1979-01-26 Analog input device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP715379A JPS55677A (en) 1979-01-26 1979-01-26 Analog input device

Publications (1)

Publication Number Publication Date
JPS55677A true JPS55677A (en) 1980-01-07

Family

ID=11658115

Family Applications (1)

Application Number Title Priority Date Filing Date
JP715379A Pending JPS55677A (en) 1979-01-26 1979-01-26 Analog input device

Country Status (1)

Country Link
JP (1) JPS55677A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4931707A (en) * 1989-08-14 1990-06-05 General Motors Corporation Impedance matching circuit

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4931707A (en) * 1989-08-14 1990-06-05 General Motors Corporation Impedance matching circuit

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