JPS5559588A - Printing system - Google Patents

Printing system

Info

Publication number
JPS5559588A
JPS5559588A JP13241078A JP13241078A JPS5559588A JP S5559588 A JPS5559588 A JP S5559588A JP 13241078 A JP13241078 A JP 13241078A JP 13241078 A JP13241078 A JP 13241078A JP S5559588 A JPS5559588 A JP S5559588A
Authority
JP
Japan
Prior art keywords
printer
signal
gate
signals
mawmd
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP13241078A
Other languages
Japanese (ja)
Inventor
Shigeru Toyomura
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Canon Inc
Original Assignee
Canon Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Canon Inc filed Critical Canon Inc
Priority to JP13241078A priority Critical patent/JPS5559588A/en
Publication of JPS5559588A publication Critical patent/JPS5559588A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE: To obtain plural sheet of record by using plural units of the printer and then giving a simultaneous printing of the same or partially same data to each recording paper while securing the synchronism among those printers.
CONSTITUTION: Printer F1 gives the connection via drive circuits D1 and E1 between driving signals MAWMD sent from arithmetic control part C anc control signals PSL and CSL each. As printer F2 is synchronized with printer F1, signals MAWMD are connected via gates G4WG7. The output of AND gate G1 turns to the set input of the FF; while the output of AND gate G2 becomes the reset input respectively. When the FF is set, stepping motor driving signal MA and MC phase feature 1 and the MB and MD phase is 0 eath to printer F2 via gates G4WG7. And stepping motor M is stopped forcedly. At the same time, input signal W-SW to be applied to control part C gives the logic product to signal W-SW2 sent from F1 via gate G8, and signal C-SW obtains the logic product between C-SW1 from F1 and C-SW2 from F2 to then supply it to part C.
COPYRIGHT: (C)1980,JPO&Japio
JP13241078A 1978-10-27 1978-10-27 Printing system Pending JPS5559588A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP13241078A JPS5559588A (en) 1978-10-27 1978-10-27 Printing system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP13241078A JPS5559588A (en) 1978-10-27 1978-10-27 Printing system

Publications (1)

Publication Number Publication Date
JPS5559588A true JPS5559588A (en) 1980-05-06

Family

ID=15080727

Family Applications (1)

Application Number Title Priority Date Filing Date
JP13241078A Pending JPS5559588A (en) 1978-10-27 1978-10-27 Printing system

Country Status (1)

Country Link
JP (1) JPS5559588A (en)

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5336316A (en) * 1976-09-14 1978-04-04 Eikou Bijinesumashin Kk Printer
JPS5361921A (en) * 1976-11-15 1978-06-02 Seiko Epson Corp Control method for printer

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5336316A (en) * 1976-09-14 1978-04-04 Eikou Bijinesumashin Kk Printer
JPS5361921A (en) * 1976-11-15 1978-06-02 Seiko Epson Corp Control method for printer

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