JPS5559580A - Arithmetic control unit - Google Patents

Arithmetic control unit

Info

Publication number
JPS5559580A
JPS5559580A JP13255378A JP13255378A JPS5559580A JP S5559580 A JPS5559580 A JP S5559580A JP 13255378 A JP13255378 A JP 13255378A JP 13255378 A JP13255378 A JP 13255378A JP S5559580 A JPS5559580 A JP S5559580A
Authority
JP
Japan
Prior art keywords
time
output
input
signal
interruption
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP13255378A
Other languages
Japanese (ja)
Inventor
Hiroichi Yamamoto
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Tokyo Shibaura Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp, Tokyo Shibaura Electric Co Ltd filed Critical Toshiba Corp
Priority to JP13255378A priority Critical patent/JPS5559580A/en
Publication of JPS5559580A publication Critical patent/JPS5559580A/en
Pending legal-status Critical Current

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Abstract

PURPOSE: To obtain an arithmetic control unit which can increase the control accuracy by knowing the lapse of time from the time point when the interruption of the interruption input signal is generated and thus knowing the input and output control method to be given after the time elapsed.
CONSTITUTION: The output of time counter circuit 16 is connected as the input of digital input circuit B17 with interruption input signal 14 generated used as the start signal, and the output of circuit B17 is supplied to arithmetic control part 2 through input/output bus 13. Part 2 recognizes the time lapse since occurrence of the interruption by reading digital input signal 5 or analog signal 6 or reading digital output signal 9 or analog output signal 10 immediately before output via circuit B17, and then carries out the process program corresponding to the time elapsed. In other words, the elapsed time is read in, and such decision can be given that the data read in is made ineffective or the control output is inhibited and others in case the elapsed time exceeds the limit time.
COPYRIGHT: (C)1980,JPO&Japio
JP13255378A 1978-10-30 1978-10-30 Arithmetic control unit Pending JPS5559580A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP13255378A JPS5559580A (en) 1978-10-30 1978-10-30 Arithmetic control unit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP13255378A JPS5559580A (en) 1978-10-30 1978-10-30 Arithmetic control unit

Publications (1)

Publication Number Publication Date
JPS5559580A true JPS5559580A (en) 1980-05-06

Family

ID=15083971

Family Applications (1)

Application Number Title Priority Date Filing Date
JP13255378A Pending JPS5559580A (en) 1978-10-30 1978-10-30 Arithmetic control unit

Country Status (1)

Country Link
JP (1) JPS5559580A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO1985004496A1 (en) * 1984-03-22 1985-10-10 Fanuc Ltd Analog input control system

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO1985004496A1 (en) * 1984-03-22 1985-10-10 Fanuc Ltd Analog input control system

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