JPS555513A - Data transmission unit - Google Patents
Data transmission unitInfo
- Publication number
- JPS555513A JPS555513A JP7770978A JP7770978A JPS555513A JP S555513 A JPS555513 A JP S555513A JP 7770978 A JP7770978 A JP 7770978A JP 7770978 A JP7770978 A JP 7770978A JP S555513 A JPS555513 A JP S555513A
- Authority
- JP
- Japan
- Prior art keywords
- signal
- fed
- counter
- gate
- level
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L27/00—Modulated-carrier systems
- H04L27/10—Frequency-modulated carrier systems, i.e. using frequency-shift keying
- H04L27/12—Modulator circuits; Transmitter circuits
- H04L27/122—Modulator circuits; Transmitter circuits using digital generation of carrier signals
Landscapes
- Engineering & Computer Science (AREA)
- Computer Networks & Wireless Communication (AREA)
- Signal Processing (AREA)
- Dc Digital Transmission (AREA)
- Digital Transmission Methods That Use Modulated Carrier Waves (AREA)
Abstract
PURPOSE:To enable to discriminate the digital signal corresponding to the carrier, by synchronizing the time of shift for the modulation signal to the time point when a half or one wave of the carrier corresponding to each level of the modulation signal is finished. CONSTITUTION:The digital signal train in binary number for the transmission is memorized in the memory circuit 1 and the output is fed to the D type FF2. The FF2 feeds one signal level to the AND gate 3 when the signal fed is 0 signal and to the gate 4 when 1 signal. The means C outputting the carrier having each frequency corresponding to the level of the modulation signal delivers the signal in frequency f1 or f2 when 1 signal is fed to the AND gate 3 or 4, to the counter 7. When the signal in frequency f1 or f2 is inputted to the counter 7, the pulses of 0 to 2<n> are counted and the count value is outputted. The sinusoidal synthesis circuit 9 outputs the sinusoidal wave of one period every time this signal is received. The output of the counter 7 is fed also to FF2 to shift the signal fetched to FF2 and to fetch the next signal from the circuit 1.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP7770978A JPS555513A (en) | 1978-06-27 | 1978-06-27 | Data transmission unit |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP7770978A JPS555513A (en) | 1978-06-27 | 1978-06-27 | Data transmission unit |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS555513A true JPS555513A (en) | 1980-01-16 |
Family
ID=13641413
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP7770978A Pending JPS555513A (en) | 1978-06-27 | 1978-06-27 | Data transmission unit |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS555513A (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS59152761A (en) * | 1983-02-18 | 1984-08-31 | Sumitomo Electric Ind Ltd | Digital fsk modulating circuit |
-
1978
- 1978-06-27 JP JP7770978A patent/JPS555513A/en active Pending
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS59152761A (en) * | 1983-02-18 | 1984-08-31 | Sumitomo Electric Ind Ltd | Digital fsk modulating circuit |
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