JPS5550649A - Preparation of resin sealing type semiconductor device - Google Patents

Preparation of resin sealing type semiconductor device

Info

Publication number
JPS5550649A
JPS5550649A JP12384278A JP12384278A JPS5550649A JP S5550649 A JPS5550649 A JP S5550649A JP 12384278 A JP12384278 A JP 12384278A JP 12384278 A JP12384278 A JP 12384278A JP S5550649 A JPS5550649 A JP S5550649A
Authority
JP
Japan
Prior art keywords
portions
sealing
heated
resin
semiconductor device
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP12384278A
Other languages
Japanese (ja)
Other versions
JPS5940289B2 (en
Inventor
Naokuni Hata
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electronics Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electronics Corp filed Critical Matsushita Electronics Corp
Priority to JP12384278A priority Critical patent/JPS5940289B2/en
Publication of JPS5550649A publication Critical patent/JPS5550649A/en
Publication of JPS5940289B2 publication Critical patent/JPS5940289B2/en
Expired legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93—Batch processes
    • H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)

Abstract

PURPOSE:To continuously assemble a huge filmy lead frame including resin sealing work in a process that winds the frame in one direction, by forming the frame in a roll-like shape. CONSTITUTION:A lead frame that semiconductor element substrates 20 are installed and connection 21 is completed is heated 18 at a primary sealing portion. Powdered epoxy resin 16 bubbled by sending in 19 air from a bottom of a vessel 17 contacts with element portions heated and primarily coats the portions with resin 22. Sealing portions are mounted in shapes that continue at two or three locations and the element portions are sealed in multilayer shapes. The element portions are arranged in a void portion of metal molds 23, 24 for projection molding at approximate 150 deg.C, powdered, thermal plastic resin 26 is projected to the void from a hole of a projecting body 25 and the element portions are secondarily sealed. The portions are actually wound every primary and secondary sealing and treated because the portions are heated after each sealing process and must be cured. Thus, sealing shells 27 are made up, a common connecting portion 1 and a bridging thin strip 5 are cut and removed and several semiconductor device is obtained.
JP12384278A 1978-10-06 1978-10-06 Manufacturing method for resin-sealed semiconductor device Expired JPS5940289B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP12384278A JPS5940289B2 (en) 1978-10-06 1978-10-06 Manufacturing method for resin-sealed semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP12384278A JPS5940289B2 (en) 1978-10-06 1978-10-06 Manufacturing method for resin-sealed semiconductor device

Publications (2)

Publication Number Publication Date
JPS5550649A true JPS5550649A (en) 1980-04-12
JPS5940289B2 JPS5940289B2 (en) 1984-09-29

Family

ID=14870729

Family Applications (1)

Application Number Title Priority Date Filing Date
JP12384278A Expired JPS5940289B2 (en) 1978-10-06 1978-10-06 Manufacturing method for resin-sealed semiconductor device

Country Status (1)

Country Link
JP (1) JPS5940289B2 (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59204245A (en) * 1983-05-06 1984-11-19 Mitsubishi Electric Corp Resin sealing process of semicondutor device

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59204245A (en) * 1983-05-06 1984-11-19 Mitsubishi Electric Corp Resin sealing process of semicondutor device
JPS6361775B2 (en) * 1983-05-06 1988-11-30

Also Published As

Publication number Publication date
JPS5940289B2 (en) 1984-09-29

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