JPS55500230A - - Google Patents

Info

Publication number
JPS55500230A
JPS55500230A JP50064079A JP50064079A JPS55500230A JP S55500230 A JPS55500230 A JP S55500230A JP 50064079 A JP50064079 A JP 50064079A JP 50064079 A JP50064079 A JP 50064079A JP S55500230 A JPS55500230 A JP S55500230A
Authority
JP
Japan
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP50064079A
Other languages
Japanese (ja)
Other versions
JPS6255236B2 (cg-RX-API-DMAC10.html
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Publication of JPS55500230A publication Critical patent/JPS55500230A/ja
Publication of JPS6255236B2 publication Critical patent/JPS6255236B2/ja
Expired legal-status Critical Current

Links

Classifications

    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C19/00Digital stores in which the information is moved stepwise, e.g. shift registers
    • G11C19/28Digital stores in which the information is moved stepwise, e.g. shift registers using semiconductor elements
    • G11C19/282Digital stores in which the information is moved stepwise, e.g. shift registers using semiconductor elements with charge storage in a depletion layer, i.e. charge coupled devices [CCD]
    • GPHYSICS
    • G06COMPUTING OR CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38Information transfer, e.g. on bus
    • G06F13/42Bus transfer protocol, e.g. handshake; Synchronisation
    • G06F13/4204Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus
    • G06F13/4234Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus being a memory bus
    • G06F13/4243Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus being a memory bus with synchronous protocol
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C19/00Digital stores in which the information is moved stepwise, e.g. shift registers
    • G11C19/28Digital stores in which the information is moved stepwise, e.g. shift registers using semiconductor elements
    • G11C19/287Organisation of a multiplicity of shift registers
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C5/00Details of stores covered by group G11C11/00
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C5/00Details of stores covered by group G11C11/00
    • G11C5/06Arrangements for interconnecting storage elements electrically, e.g. by wiring
    • G11C5/066Means for reducing external access-lines for a semiconductor memory clip, e.g. by multiplexing at least address and data signals
    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03KPULSE TECHNIQUE
    • H03K17/00Electronic switching or gating, i.e. not by contact-making and –breaking
    • H03K17/30Modifications for providing a predetermined threshold before switching
    • H03K17/302Modifications for providing a predetermined threshold before switching in field-effect transistor switches
    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02DCLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00Energy efficient computing, e.g. low power processors, power management or thermal management

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Static Random-Access Memory (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Dram (AREA)
JP54500640A 1978-04-11 1979-03-19 Expired JPS6255236B2 (cg-RX-API-DMAC10.html)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US05/895,328 US4145760A (en) 1978-04-11 1978-04-11 Memory device having a reduced number of pins

Publications (2)

Publication Number Publication Date
JPS55500230A true JPS55500230A (cg-RX-API-DMAC10.html) 1980-04-17
JPS6255236B2 JPS6255236B2 (cg-RX-API-DMAC10.html) 1987-11-18

Family

ID=25404344

Family Applications (1)

Application Number Title Priority Date Filing Date
JP54500640A Expired JPS6255236B2 (cg-RX-API-DMAC10.html) 1978-04-11 1979-03-19

Country Status (5)

Country Link
US (1) US4145760A (cg-RX-API-DMAC10.html)
JP (1) JPS6255236B2 (cg-RX-API-DMAC10.html)
DE (1) DE2947100C2 (cg-RX-API-DMAC10.html)
GB (1) GB2037521B (cg-RX-API-DMAC10.html)
WO (1) WO1979000914A1 (cg-RX-API-DMAC10.html)

Families Citing this family (26)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4148099A (en) * 1978-04-11 1979-04-03 Ncr Corporation Memory device having a minimum number of pins
US4145760A (en) * 1978-04-11 1979-03-20 Ncr Corporation Memory device having a reduced number of pins
US4330842A (en) * 1978-09-05 1982-05-18 Daniels R Gary Valid memory address pin elimination
US4503491A (en) * 1981-06-29 1985-03-05 Matsushita Electric Industrial Co., Ltd. Computer with expanded addressing capability
US4620707A (en) * 1983-06-27 1986-11-04 Syntex Computer Systems, Inc. Non-volatile reprogrammable ram cartridge
US4654789A (en) * 1984-04-04 1987-03-31 Honeywell Information Systems Inc. LSI microprocessor chip with backward pin compatibility
US4573141A (en) * 1984-04-12 1986-02-25 General Electric Company Memory interface for communicating between two storage media having incompatible data formats
JPS6166295A (ja) * 1984-09-10 1986-04-05 Nec Corp 半導体メモリ
US4677548A (en) * 1984-09-26 1987-06-30 Honeywell Information Systems Inc. LSI microprocessor chip with backward pin compatibility and forward expandable functionality
US4654829A (en) * 1984-12-17 1987-03-31 Dallas Semiconductor Corporation Portable, non-volatile read/write memory module
DE3721483A1 (de) * 1987-06-30 1989-01-12 Connec Ag Befestigungsvorrichtung mit einem klemmverschluss zum loesbaren angreifen an profilen
JPH01100788A (ja) * 1987-10-13 1989-04-19 Hitachi Ltd 半導体集積回路装置
JP2621894B2 (ja) * 1987-12-26 1997-06-18 株式会社東芝 マイクロコンピュータ
DE69121382T2 (de) * 1991-01-17 1997-02-27 Philips Electronics Nv Emulator zur Emulation eines verbindungsloses Mikrokontroller und Mikrokontroller zur Verwendung in einem solchen Emulator
US5511024A (en) * 1993-06-02 1996-04-23 Rambus, Inc. Dynamic random access memory system
KR960703275A (ko) * 1994-04-18 1996-06-19 쟈끄 위베르 가이 전자메모리장치(electronic memory device)
AU6502896A (en) * 1995-07-20 1997-02-18 Dallas Semiconductor Corporation Single chip microprocessor, math co-processor, random number generator, real-time clock and ram having a one-wire interface
KR0170905B1 (ko) * 1995-11-06 1999-03-30 김주용 디램
US5881121A (en) * 1997-02-13 1999-03-09 Cypress Semiconductor Corp. One-pin shift register interface
EP1019912A2 (en) 1997-10-10 2000-07-19 Rambus Incorporated Apparatus and method for pipelined memory operations
US7454644B2 (en) 2001-06-15 2008-11-18 Stmicroelectronics Sa Integrated circuit with low current consumption having a one wire communication interface
EP2671228B1 (en) * 2011-02-01 2022-04-13 3M Innovative Properties Company A passive interface for an electronic memory device
CN109542465B (zh) * 2018-10-29 2024-03-19 天浪创新科技(深圳)有限公司 集成电路芯片的数据写入方法、系统、装置、设备及介质
JP6799143B2 (ja) * 2018-04-24 2020-12-09 天浪▲創▼新科技(深▲セン▼)有限公司 集積回路チップのデータ書き込み方法、システム、装置、デバイスおよび媒体
CN108363581B (zh) * 2018-04-24 2023-12-01 天浪创新科技(深圳)有限公司 集成电路芯片的数据写入方法、系统、装置、设备及介质
CN109213718B (zh) * 2018-11-12 2024-01-26 上海艾为电子技术股份有限公司 一种i2c通信装置及i2c通信设备

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3786277A (en) * 1971-07-22 1974-01-15 Siemens Ag Circuit arrangement of mos transistors operating according to the dynamic principle for decoding the addresses for an mos memory
US3851221A (en) * 1972-11-30 1974-11-26 P Beaulieu Integrated circuit package
US4007452A (en) * 1975-07-28 1977-02-08 Intel Corporation Wafer scale integration system
US4044339A (en) * 1975-12-15 1977-08-23 Honeywell Inc. Block oriented random access memory
US4148099A (en) * 1978-04-11 1979-04-03 Ncr Corporation Memory device having a minimum number of pins
US4145760A (en) * 1978-04-11 1979-03-20 Ncr Corporation Memory device having a reduced number of pins

Also Published As

Publication number Publication date
DE2947100C2 (de) 1985-03-07
GB2037521A (en) 1980-07-09
DE2947100T1 (de) 1982-01-28
JPS6255236B2 (cg-RX-API-DMAC10.html) 1987-11-18
WO1979000914A1 (en) 1979-11-15
GB2037521B (en) 1983-01-26
US4145760A (en) 1979-03-20

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