JPS5546598A - Durable memory array - Google Patents

Durable memory array

Info

Publication number
JPS5546598A
JPS5546598A JP12524779A JP12524779A JPS5546598A JP S5546598 A JPS5546598 A JP S5546598A JP 12524779 A JP12524779 A JP 12524779A JP 12524779 A JP12524779 A JP 12524779A JP S5546598 A JPS5546598 A JP S5546598A
Authority
JP
Japan
Prior art keywords
memory array
durable memory
durable
array
memory
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP12524779A
Other languages
English (en)
Other versions
JPS5732514B2 (ja
Inventor
Ten Suu Shien
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
RCA Corp
Original Assignee
RCA Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by RCA Corp filed Critical RCA Corp
Publication of JPS5546598A publication Critical patent/JPS5546598A/ja
Publication of JPS5732514B2 publication Critical patent/JPS5732514B2/ja
Granted legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/04—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
    • G11C16/0408—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells containing floating gate transistors
    • G11C16/0425—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells containing floating gate transistors comprising cells containing a merged floating gate and select transistor
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B69/00—Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices
JP12524779A 1978-09-28 1979-09-27 Durable memory array Granted JPS5546598A (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US94672278A 1978-09-28 1978-09-28

Publications (2)

Publication Number Publication Date
JPS5546598A true JPS5546598A (en) 1980-04-01
JPS5732514B2 JPS5732514B2 (ja) 1982-07-12

Family

ID=25484885

Family Applications (1)

Application Number Title Priority Date Filing Date
JP12524779A Granted JPS5546598A (en) 1978-09-28 1979-09-27 Durable memory array

Country Status (6)

Country Link
JP (1) JPS5546598A (ja)
DE (1) DE2937952C2 (ja)
FR (1) FR2437676A1 (ja)
GB (1) GB2032687B (ja)
IT (1) IT1122538B (ja)
SE (1) SE7907193L (ja)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6325981A (ja) * 1986-05-30 1988-02-03 アトメル・コーポレイション 電気的にブロツク消去可能なｅｅｐｒｏｍ
US9030877B2 (en) 2007-08-30 2015-05-12 Infineon Technologies Ag Memory cell arrangement, method for controlling a memory cell, memory array and electronic device

Families Citing this family (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4328565A (en) 1980-04-07 1982-05-04 Eliyahou Harari Non-volatile eprom with increased efficiency
US4409723A (en) * 1980-04-07 1983-10-18 Eliyahou Harari Method of forming non-volatile EPROM and EEPROM with increased efficiency
DE3141390A1 (de) * 1981-10-19 1983-04-28 Deutsche Itt Industries Gmbh, 7800 Freiburg Floating-gate-speicherzelle, bei der das schreiben und loeschen durch injektion heisser ladungstraeger erfolgt
FR2524714B1 (fr) * 1982-04-01 1986-05-02 Suwa Seikosha Kk Transistor a couche mince
US4639893A (en) * 1984-05-15 1987-01-27 Wafer Scale Integration, Inc. Self-aligned split gate EPROM
US4868629A (en) * 1984-05-15 1989-09-19 Waferscale Integration, Inc. Self-aligned split gate EPROM
US4795719A (en) * 1984-05-15 1989-01-03 Waferscale Integration, Inc. Self-aligned split gate eprom process
FR2621737B1 (fr) * 1987-10-09 1991-04-05 Thomson Semiconducteurs Memoire en circuit integre
US5087584A (en) * 1990-04-30 1992-02-11 Intel Corporation Process for fabricating a contactless floating gate memory array utilizing wordline trench vias
KR100241524B1 (ko) * 1996-12-28 2000-02-01 김영환 플래쉬 메모리 셀

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS53108247A (en) * 1976-12-27 1978-09-20 Texas Instruments Inc Electrically programmable floating gate semiconductor memory

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3728695A (en) * 1971-10-06 1973-04-17 Intel Corp Random-access floating gate mos memory array
DE2525097C3 (de) * 1975-06-05 1982-08-05 Siemens AG, 1000 Berlin und 8000 München Verfahren zum Betrieb eines n-Kanal-Speicher-FET
AT365000B (de) * 1974-09-20 1981-11-25 Siemens Ag N-kanal-speicher-fet
DE2643948C2 (de) * 1976-09-29 1981-10-15 Siemens AG, 1000 Berlin und 8000 München In einer Matrix angeordnete Speicher-FETs und Verfahren zu ihrer Herstellung

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS53108247A (en) * 1976-12-27 1978-09-20 Texas Instruments Inc Electrically programmable floating gate semiconductor memory

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6325981A (ja) * 1986-05-30 1988-02-03 アトメル・コーポレイション 電気的にブロツク消去可能なｅｅｐｒｏｍ
US9030877B2 (en) 2007-08-30 2015-05-12 Infineon Technologies Ag Memory cell arrangement, method for controlling a memory cell, memory array and electronic device

Also Published As

Publication number Publication date
FR2437676B1 (ja) 1982-12-17
IT1122538B (it) 1986-04-23
GB2032687B (en) 1983-03-23
SE7907193L (sv) 1980-03-29
GB2032687A (en) 1980-05-08
FR2437676A1 (fr) 1980-04-25
JPS5732514B2 (ja) 1982-07-12
IT7925552A0 (it) 1979-09-07
DE2937952A1 (de) 1980-04-03
DE2937952C2 (de) 1983-04-14

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