JPS5545150A - Pcm recorder - Google Patents

Pcm recorder

Info

Publication number
JPS5545150A
JPS5545150A JP11793378A JP11793378A JPS5545150A JP S5545150 A JPS5545150 A JP S5545150A JP 11793378 A JP11793378 A JP 11793378A JP 11793378 A JP11793378 A JP 11793378A JP S5545150 A JPS5545150 A JP S5545150A
Authority
JP
Japan
Prior art keywords
signal
pcm
data
synchronizing
memory
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP11793378A
Other languages
Japanese (ja)
Other versions
JPS6128184B2 (en
Inventor
Hiroyuki Kimura
Yasunori Kanazawa
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP11793378A priority Critical patent/JPS5545150A/en
Publication of JPS5545150A publication Critical patent/JPS5545150A/en
Publication of JPS6128184B2 publication Critical patent/JPS6128184B2/ja
Granted legal-status Critical Current

Links

Abstract

PURPOSE: To prevent destruction of data, used to expand a PCM signal, in a memory by resetting a memory read address register, etc., depending upon the logical product of a PCM reproduced synchronizing signal and data read end signal.
CONSTITUTION: The set output of FF 51 set by a vertical synchronizing signal separated from a PCM reproduced signal and an end signal synchronizing with clocks generated at the one-block read end of address register 55 reading data from memory 56 are AND-ed by AND gate 54 to reset the system together with FF 51 and register 55, thereby putting the system in its initial state. Therefore, the system is reset synchronizing with clocks by the end signal right after the generation of the vertical synchronizing signal only in a fixed period, so that the expansion of the PCM regenerated signal, etc., can be done without the destruction of data due to the generation of error data.
COPYRIGHT: (C)1980,JPO&Japio
JP11793378A 1978-09-27 1978-09-27 Pcm recorder Granted JPS5545150A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP11793378A JPS5545150A (en) 1978-09-27 1978-09-27 Pcm recorder

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP11793378A JPS5545150A (en) 1978-09-27 1978-09-27 Pcm recorder

Publications (2)

Publication Number Publication Date
JPS5545150A true JPS5545150A (en) 1980-03-29
JPS6128184B2 JPS6128184B2 (en) 1986-06-28

Family

ID=14723791

Family Applications (1)

Application Number Title Priority Date Filing Date
JP11793378A Granted JPS5545150A (en) 1978-09-27 1978-09-27 Pcm recorder

Country Status (1)

Country Link
JP (1) JPS5545150A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6195864U (en) * 1984-11-29 1986-06-20

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6195864U (en) * 1984-11-29 1986-06-20

Also Published As

Publication number Publication date
JPS6128184B2 (en) 1986-06-28

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