JPS554162A - Channel selector - Google Patents

Channel selector

Info

Publication number
JPS554162A
JPS554162A JP7720378A JP7720378A JPS554162A JP S554162 A JPS554162 A JP S554162A JP 7720378 A JP7720378 A JP 7720378A JP 7720378 A JP7720378 A JP 7720378A JP S554162 A JPS554162 A JP S554162A
Authority
JP
Japan
Prior art keywords
channel
ram19
bits
channel selection
selection voltages
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP7720378A
Other languages
Japanese (ja)
Inventor
Minoru Nagai
Masami Nakamura
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sony Corp
Original Assignee
Sony Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sony Corp filed Critical Sony Corp
Priority to JP7720378A priority Critical patent/JPS554162A/en
Publication of JPS554162A publication Critical patent/JPS554162A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE: To prevent a channel different from a display channel from being selected by equipping the channel selector of a television receiver, using an electronic tuner, with two memory units stored with channel selection voltages.
CONSTITUTION: A channel selected by channel selection operation part 4 is displayed by display unit 7, and channel selection voltages are read out from two RAM18 and RAM19 and supplied to tuner 1 via D-A converter 2. In this case, channel selection voltages of all channels are made into digital signals of 12 bits; for example, upper six bits are stored in RAM18 and lower six bits are in RAM19. Then, the output of RAM19 is supplied to converter 2 via up-down counter 20 and through the operations of fine-tuning switches 10 and 11, counter 20 corrects lower- bit information, so that memory information in RAM19 will be rewritten. Therefore, since upper six bits are fixed in ROM18, adjustment ranges of switches 10 and 11 narrow, and consequently, a channel different from a display channel will never be selected.
COPYRIGHT: (C)1980,JPO&Japio
JP7720378A 1978-06-26 1978-06-26 Channel selector Pending JPS554162A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP7720378A JPS554162A (en) 1978-06-26 1978-06-26 Channel selector

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP7720378A JPS554162A (en) 1978-06-26 1978-06-26 Channel selector

Publications (1)

Publication Number Publication Date
JPS554162A true JPS554162A (en) 1980-01-12

Family

ID=13627260

Family Applications (1)

Application Number Title Priority Date Filing Date
JP7720378A Pending JPS554162A (en) 1978-06-26 1978-06-26 Channel selector

Country Status (1)

Country Link
JP (1) JPS554162A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5981130U (en) * 1982-11-22 1984-06-01 株式会社光電製作所 Synthesizer receiver frequency setter

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5981130U (en) * 1982-11-22 1984-06-01 株式会社光電製作所 Synthesizer receiver frequency setter

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