JPS554125A - Demodulator circuit - Google Patents

Demodulator circuit

Info

Publication number
JPS554125A
JPS554125A JP7684378A JP7684378A JPS554125A JP S554125 A JPS554125 A JP S554125A JP 7684378 A JP7684378 A JP 7684378A JP 7684378 A JP7684378 A JP 7684378A JP S554125 A JPS554125 A JP S554125A
Authority
JP
Japan
Prior art keywords
circuit
carrier
signal
discrimination
demodulated
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP7684378A
Other languages
Japanese (ja)
Inventor
Ichiro Takase
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP7684378A priority Critical patent/JPS554125A/en
Publication of JPS554125A publication Critical patent/JPS554125A/en
Pending legal-status Critical Current

Links

Landscapes

  • Dc Digital Transmission (AREA)
  • Digital Transmission Methods That Use Modulated Carrier Waves (AREA)

Abstract

PURPOSE: To make it possible to obtain a demodulation signal with a carrier component of higher degree removed, by supplying a signal phase-detected and demodulated to a discrimination circuit which makes a carrier multiplied by two by a carrier extraction circuit into a discrimination clock.
CONSTITUTION: A modulated wave arriving at input terminal 501 is branched into two; one wave, after passing through doubling circuit 502, resonator 503, slicer 504, and halving circuit 505, components of the carrier extraction circuit, and the other are both inputted to phase detector 506, where the both are phase-detected. On receiving the signal pase-detected and demodulated, discrimination circuit 507 which makes a carrier doubled by the carrier extraction circuit into a discrimination clock outputs the demodulated signal from the output terminal. Consequently, an excellent demodulated signal can be obtained by removing a carrier component of higher degree after the phase detection by using the discrimination circuit.
COPYRIGHT: (C)1980,JPO&Japio
JP7684378A 1978-06-23 1978-06-23 Demodulator circuit Pending JPS554125A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP7684378A JPS554125A (en) 1978-06-23 1978-06-23 Demodulator circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP7684378A JPS554125A (en) 1978-06-23 1978-06-23 Demodulator circuit

Publications (1)

Publication Number Publication Date
JPS554125A true JPS554125A (en) 1980-01-12

Family

ID=13616935

Family Applications (1)

Application Number Title Priority Date Filing Date
JP7684378A Pending JPS554125A (en) 1978-06-23 1978-06-23 Demodulator circuit

Country Status (1)

Country Link
JP (1) JPS554125A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4760344A (en) * 1986-02-07 1988-07-26 Hitachi, Ltd. Phase shift keying signal demodulation method and apparatus

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4760344A (en) * 1986-02-07 1988-07-26 Hitachi, Ltd. Phase shift keying signal demodulation method and apparatus

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