JPS5537666A - Information transfer controller - Google Patents

Information transfer controller

Info

Publication number
JPS5537666A
JPS5537666A JP11084678A JP11084678A JPS5537666A JP S5537666 A JPS5537666 A JP S5537666A JP 11084678 A JP11084678 A JP 11084678A JP 11084678 A JP11084678 A JP 11084678A JP S5537666 A JPS5537666 A JP S5537666A
Authority
JP
Japan
Prior art keywords
transfer
processors
registers
control
requests
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP11084678A
Other languages
Japanese (ja)
Inventor
Shuji Miki
Takahiko Yamada
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Nippon Telegraph and Telephone Corp
Original Assignee
Nippon Telegraph and Telephone Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nippon Telegraph and Telephone Corp filed Critical Nippon Telegraph and Telephone Corp
Priority to JP11084678A priority Critical patent/JPS5537666A/en
Publication of JPS5537666A publication Critical patent/JPS5537666A/en
Pending legal-status Critical Current

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  • Multi Processors (AREA)

Abstract

PURPOSE: To assign the processing performance of a processor to a maximum internal process by sequentially accepting and sending transfer requests from several processors to a control register and then by registering them again by transfer objects for transfer control.
CONSTITUTION: In formation transfer unit 1 and 2 control information transfer among processors 3...8 through interface lines 12 and 13 and that between processors 3...8 and input-output equipments 16...21 through interface lines 12 and 13, and 22 and 23, and data channel 14 and 15. Then, reception control register Q31 registers sequentially transfer requests from processors 3-8 and registers Q33...Q36 registers again the transfer requests registered in reigster Q31 by transfer objects. Those transfer requests are transferred in sequence by communication control registers 40...43. Consequently, the processing performance of processors is assigned to the maximun internal process.
COPYRIGHT: (C)1980,JPO&Japio
JP11084678A 1978-09-09 1978-09-09 Information transfer controller Pending JPS5537666A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP11084678A JPS5537666A (en) 1978-09-09 1978-09-09 Information transfer controller

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP11084678A JPS5537666A (en) 1978-09-09 1978-09-09 Information transfer controller

Publications (1)

Publication Number Publication Date
JPS5537666A true JPS5537666A (en) 1980-03-15

Family

ID=14546139

Family Applications (1)

Application Number Title Priority Date Filing Date
JP11084678A Pending JPS5537666A (en) 1978-09-09 1978-09-09 Information transfer controller

Country Status (1)

Country Link
JP (1) JPS5537666A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61202258A (en) * 1985-03-06 1986-09-08 Fujitsu Ltd Channel processing system

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS53101207A (en) * 1977-02-16 1978-09-04 Fujitsu Ltd Electronic exchange system

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS53101207A (en) * 1977-02-16 1978-09-04 Fujitsu Ltd Electronic exchange system

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61202258A (en) * 1985-03-06 1986-09-08 Fujitsu Ltd Channel processing system
JPH0544696B2 (en) * 1985-03-06 1993-07-07 Fujitsu Ltd

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