JPS5537618A - Memory controller - Google Patents

Memory controller

Info

Publication number
JPS5537618A
JPS5537618A JP10935678A JP10935678A JPS5537618A JP S5537618 A JPS5537618 A JP S5537618A JP 10935678 A JP10935678 A JP 10935678A JP 10935678 A JP10935678 A JP 10935678A JP S5537618 A JPS5537618 A JP S5537618A
Authority
JP
Japan
Prior art keywords
data
file
stored
address
mem3
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP10935678A
Other languages
Japanese (ja)
Inventor
Hiroyuki Koarai
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP10935678A priority Critical patent/JPS5537618A/en
Publication of JPS5537618A publication Critical patent/JPS5537618A/en
Pending legal-status Critical Current

Links

Landscapes

  • Information Retrieval, Db Structures And Fs Structures Therefor (AREA)
  • Signal Processing For Digital Recording And Reproducing (AREA)

Abstract

PURPOSE: To improve processing time by allowing access to a file in case that re- access to the file is attained, read data agrees with stored data.
CONSTITUTION: According to assigned address FILN, file control part FC drives file FIL to read data in the corresponding address and then to store it in memories MEM1 and MEM2 and on the basis of the data stored in memory (MEM1), CPU generates new update data and store it in MEM3. To write data stored (MEM3) in FILN of FIL, CPU gives FC FILN as a write address. Then, the read data is compared with stored (MEM2) data read at the time of 1st access and when the both agree, AND gate A2 is opened to store data received from MEM3 into the address of retrieved FIL.
COPYRIGHT: (C)1980,JPO&Japio
JP10935678A 1978-09-06 1978-09-06 Memory controller Pending JPS5537618A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP10935678A JPS5537618A (en) 1978-09-06 1978-09-06 Memory controller

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP10935678A JPS5537618A (en) 1978-09-06 1978-09-06 Memory controller

Publications (1)

Publication Number Publication Date
JPS5537618A true JPS5537618A (en) 1980-03-15

Family

ID=14508141

Family Applications (1)

Application Number Title Priority Date Filing Date
JP10935678A Pending JPS5537618A (en) 1978-09-06 1978-09-06 Memory controller

Country Status (1)

Country Link
JP (1) JPS5537618A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH02165268A (en) * 1988-12-20 1990-06-26 Matsushita Electric Ind Co Ltd Document preparing device
JPH0340042A (en) * 1989-07-06 1991-02-20 Nec Corp Multiple accessing device

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH02165268A (en) * 1988-12-20 1990-06-26 Matsushita Electric Ind Co Ltd Document preparing device
JPH0340042A (en) * 1989-07-06 1991-02-20 Nec Corp Multiple accessing device

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