JPS5532407A - Servo system - Google Patents

Servo system

Info

Publication number
JPS5532407A
JPS5532407A JP10277878A JP10277878A JPS5532407A JP S5532407 A JPS5532407 A JP S5532407A JP 10277878 A JP10277878 A JP 10277878A JP 10277878 A JP10277878 A JP 10277878A JP S5532407 A JPS5532407 A JP S5532407A
Authority
JP
Japan
Prior art keywords
phase
counter
pulse
signal
flop
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP10277878A
Other languages
Japanese (ja)
Inventor
Tadahiko Nakamura
Kenji Nakano
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sony Corp
Original Assignee
Sony Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sony Corp filed Critical Sony Corp
Priority to JP10277878A priority Critical patent/JPS5532407A/en
Publication of JPS5532407A publication Critical patent/JPS5532407A/en
Pending legal-status Critical Current

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  • Control Of Electric Motors In General (AREA)

Abstract

PURPOSE: To dispense with a frequency compensation circuit and improve the rising property of a speed servo mechanism, by changing the locked position of the speed servo mechanism depending on a phase deviation signal.
CONSTITUTION: The phase differnce between a phase reference pulse on a terminal 102 and a pulse PGC on a terminal 100, namely, the pulse period of a flip- flop 108 is measured first by a counter 120. Then, the counter 120 generates an output MSD while intermediate clock pulses during the period of a signal FF 21 are counted. A buffer counter 126 for a phase loop generates a signal MFD which is phase difference information, thereby changing an initial value for the count of a counter 78 for detecting the velocity of a speed loop. A flip-flop 70 for generating a frequency modulation output produces a pulse of width corresponding to the magnitude of phase and velocity terms.
COPYRIGHT: (C)1980,JPO&Japio
JP10277878A 1978-08-25 1978-08-25 Servo system Pending JPS5532407A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP10277878A JPS5532407A (en) 1978-08-25 1978-08-25 Servo system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP10277878A JPS5532407A (en) 1978-08-25 1978-08-25 Servo system

Publications (1)

Publication Number Publication Date
JPS5532407A true JPS5532407A (en) 1980-03-07

Family

ID=14336598

Family Applications (1)

Application Number Title Priority Date Filing Date
JP10277878A Pending JPS5532407A (en) 1978-08-25 1978-08-25 Servo system

Country Status (1)

Country Link
JP (1) JPS5532407A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62131777A (en) * 1985-11-28 1987-06-15 Seiko Epson Corp Speed controller for motor
JPS63209492A (en) * 1987-02-26 1988-08-31 Mitsubishi Electric Corp Device for controlling phase of rotation

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62131777A (en) * 1985-11-28 1987-06-15 Seiko Epson Corp Speed controller for motor
JPS63209492A (en) * 1987-02-26 1988-08-31 Mitsubishi Electric Corp Device for controlling phase of rotation

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