JPS5532191A - Terminal control device - Google Patents

Terminal control device

Info

Publication number
JPS5532191A
JPS5532191A JP10585178A JP10585178A JPS5532191A JP S5532191 A JPS5532191 A JP S5532191A JP 10585178 A JP10585178 A JP 10585178A JP 10585178 A JP10585178 A JP 10585178A JP S5532191 A JPS5532191 A JP S5532191A
Authority
JP
Japan
Prior art keywords
address
decode
line
terminal control
bus
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP10585178A
Other languages
Japanese (ja)
Other versions
JPS5844252B2 (en
Inventor
Eiichi Kumagai
Masatoshi Horiguchi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Nippon Telegraph and Telephone Corp
Original Assignee
NEC Corp
Nippon Telegraph and Telephone Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Telegraph and Telephone Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP53105851A priority Critical patent/JPS5844252B2/en
Publication of JPS5532191A publication Critical patent/JPS5532191A/en
Publication of JPS5844252B2 publication Critical patent/JPS5844252B2/en
Expired legal-status Critical Current

Links

Landscapes

  • Memory System (AREA)
  • Data Exchanges In Wide-Area Networks (AREA)
  • Small-Scale Networks (AREA)

Abstract

PURPOSE: To prepare the half decode line in which the address line is decoded partially in advance is prepared for the exclusively used bus and the common bus, thereby to make possible the terminal control adapter to be connected to both the buses without changing the terminal control adapter into the hardware.
CONSTITUTION: In the case of connecting the address to the exclusively used bus in the address decode circuit, the indexed address is 7F81, and in the case of connecting the address to the common bus, it is 8001H. Since the upper rank 9 bit of the address line 201 has been already the half decode line 204, the lower rank 7 bit is decoded in conformity with the relative address in the half decode area. In this case, AO is put into AND gate 206 directly as input and A1 to A6 are inputted as input AND gate 206 through the inverter 205. In addition, the half decode line 204 is inputted to AND gate 206 as input. Accordingly, when the address decode circuit is connected to the exclusively used bus, the address select 207 becomes logic 1 if the address is 7F81H. When the address decode circuit is connected to the common bus, the address select becomes logic 1 if the address is 8001H.
COPYRIGHT: (C)1980,JPO&Japio
JP53105851A 1978-08-29 1978-08-29 terminal control device Expired JPS5844252B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP53105851A JPS5844252B2 (en) 1978-08-29 1978-08-29 terminal control device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP53105851A JPS5844252B2 (en) 1978-08-29 1978-08-29 terminal control device

Publications (2)

Publication Number Publication Date
JPS5532191A true JPS5532191A (en) 1980-03-06
JPS5844252B2 JPS5844252B2 (en) 1983-10-01

Family

ID=14418492

Family Applications (1)

Application Number Title Priority Date Filing Date
JP53105851A Expired JPS5844252B2 (en) 1978-08-29 1978-08-29 terminal control device

Country Status (1)

Country Link
JP (1) JPS5844252B2 (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61208152A (en) * 1985-03-12 1986-09-16 Matsushita Electronics Corp Integrated circuit

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP7170450B2 (en) 2018-07-31 2022-11-14 信越化学工業株式会社 Addition-curable silicone resin composition and semiconductor device

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS502837A (en) * 1973-05-11 1975-01-13
JPS5115336A (en) * 1974-07-29 1976-02-06 Yokogawa Electric Works Ltd
JPS5255447A (en) * 1975-10-31 1977-05-06 Toshiba Corp Microprocessor

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS502837A (en) * 1973-05-11 1975-01-13
JPS5115336A (en) * 1974-07-29 1976-02-06 Yokogawa Electric Works Ltd
JPS5255447A (en) * 1975-10-31 1977-05-06 Toshiba Corp Microprocessor

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61208152A (en) * 1985-03-12 1986-09-16 Matsushita Electronics Corp Integrated circuit

Also Published As

Publication number Publication date
JPS5844252B2 (en) 1983-10-01

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