JPS5528568A - Mfm demodulator circuit - Google Patents

Mfm demodulator circuit

Info

Publication number
JPS5528568A
JPS5528568A JP10160178A JP10160178A JPS5528568A JP S5528568 A JPS5528568 A JP S5528568A JP 10160178 A JP10160178 A JP 10160178A JP 10160178 A JP10160178 A JP 10160178A JP S5528568 A JPS5528568 A JP S5528568A
Authority
JP
Japan
Prior art keywords
zero crossover
output
nrz data
oscillator
pulse
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP10160178A
Other languages
Japanese (ja)
Inventor
Tetsuo Shimizu
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sanyo Electric Co Ltd
Original Assignee
Sanyo Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sanyo Electric Co Ltd filed Critical Sanyo Electric Co Ltd
Priority to JP10160178A priority Critical patent/JPS5528568A/en
Publication of JPS5528568A publication Critical patent/JPS5528568A/en
Pending legal-status Critical Current

Links

Classifications

    • F—MECHANICAL ENGINEERING; LIGHTING; HEATING; WEAPONS; BLASTING
    • F02—COMBUSTION ENGINES; HOT-GAS OR COMBUSTION-PRODUCT ENGINE PLANTS
    • F02B—INTERNAL-COMBUSTION PISTON ENGINES; COMBUSTION ENGINES IN GENERAL
    • F02B75/00—Other engines
    • F02B75/02—Engines characterised by their cycles, e.g. six-stroke
    • F02B2075/022—Engines characterised by their cycles, e.g. six-stroke having less than six strokes per cycle
    • F02B2075/025—Engines characterised by their cycles, e.g. six-stroke having less than six strokes per cycle two

Landscapes

  • Signal Processing For Digital Recording And Reproducing (AREA)
  • Digital Transmission Methods That Use Modulated Carrier Waves (AREA)
  • Dc Digital Transmission (AREA)

Abstract

PURPOSE: To secure the accurate demodulation for the NRZ data by locking the voltage control oscillator of the PLL at the time point when the output cycle reaches the prescribed level and in accordance with the zero crossover pulse of the NRZ reproduction data received the modified FM modulation.
CONSTITUTION: The zero crossover pulse of the reproduction NRZ data delivered by zero crossover detector 5 is turned to the pulse of 1/2 cycle T of the NRZ data via delay circuit 6 and then undergoes the phase comparison through phase comparator 7 via the AND output produced through gate 10 of the zero crossover pulse of detector 5 and the oscillation output of voltage control type oscillator 9. Thus the PLL comprising gate 10, comparator 7, oscillator 9 and others is locked when the output cycle of oscillator 9 features 1/2×T. And the phase comparison can be carried out accurately to the zero crossover pulse corresponding to the 1-center of the NRZ data as well as to the zero crossover pulse corresponding to the O-boundary of the NRZ data each. As a result, the NRZ data can be demodulated accurately via D-type FF16 driven by the clock and via the output of circuit 9 which passed through gate 14 using the division output of 1/2 divider 12.
COPYRIGHT: (C)1980,JPO&Japio
JP10160178A 1978-08-18 1978-08-18 Mfm demodulator circuit Pending JPS5528568A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP10160178A JPS5528568A (en) 1978-08-18 1978-08-18 Mfm demodulator circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP10160178A JPS5528568A (en) 1978-08-18 1978-08-18 Mfm demodulator circuit

Publications (1)

Publication Number Publication Date
JPS5528568A true JPS5528568A (en) 1980-02-29

Family

ID=14304901

Family Applications (1)

Application Number Title Priority Date Filing Date
JP10160178A Pending JPS5528568A (en) 1978-08-18 1978-08-18 Mfm demodulator circuit

Country Status (1)

Country Link
JP (1) JPS5528568A (en)

Similar Documents

Publication Publication Date Title
US3982190A (en) Phaselock circuitry with lock indication
JPS6448267A (en) Pll circuit for magnetic disk device
US4513448A (en) Low power radio synthesizer with harmonic identification feature
MY107067A (en) Automatic frequency control in the presence of data.
WO1985002966A1 (en) A phase shift keying and phase modulation transmission system
JPS5797251A (en) High speed phase lock system for digital phase locking circuit
US4656431A (en) Digital frequency discriminator
JPS5528568A (en) Mfm demodulator circuit
GB1485685A (en) Frequency locking system
JPS5528567A (en) Mfm demodulator circuit
DE3776217D1 (en) DEMODULATOR ARRANGEMENT.
DE69129316D1 (en) Phase locked loop
JPS51117860A (en) Phase lock loop
JPS5346255A (en) Pll circuit
JPS54148512A (en) Phase synchronizing circuit
JPS531448A (en) Carrier detector
JPS556965A (en) Carrier wave reproducing device
JPS5549004A (en) Phase demodulation circuit
JPS5593528A (en) Data demodulation unit
JPS5376870A (en) Temperature compensating circuit of frequency discriminator
JPS5548821A (en) Phase synchronous circuit
JPS5483752A (en) Pll frequency synthesizer system
JPS55105441A (en) Signal detection circuit
JPS54104270A (en) Carrier regenerative circuit
JPS5331950A (en) Frequency discriminator